Texas Instruments 990 Manual page 71

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Memory Array. The memory array consists of 16 TMS4033 1024-word-by-l-bit static RAM chips
arranged to provide 2048 (2K) eight-bit words of storage. Data inputs for the memory array are
produced by the memory/CRU input data register. Characters are addressed (MA,0-A) by the
memory address multiplexer, which provides the address of the present cursor location or the
next character required for screen refresh. Only 1024 ( 1 K) eight-bit words of storage are available
for the 960-character controller, while the full 2K words are available for the 1920-character
controller.
Read Data Latches. The read data latches (see figure 1-38) latch the character data output by the
memory array and provide the data to the character generator for producing dot patterns for
display on the CRT screen, and to the memory/CRU input data register as the character read at
the cursor address when the cursor is moved to a new location.
Memory Control Logic. Figures 1-39 and 1-40 show the control logic associated with the refresh
memory, and figures 1-41 through 1-43 are flowcharts for memory control logic.
The circuitry shown in figure 1-39 latches and synchronizes read and write commands from CRU
interface logic to control the writing of a character into memory for display by the CRT
monitor, and the reading of a character from memory to update the memory/CRU input data
register. Synchronization of the read and write commands from CRU interface logic is required
because the commands from the computer are asynchronous to the controller.
The circuitry shown in figure 1-40 selects the memory address. The address provided to the
memory (MA,0-10) is selected from the character address provided by the time base generator
for refresh purposes (KAD,0-10) or the current cursor address provided by the cursor address
register (CAD,0-10). The cursor address register output is selected to write a new character at the
cursor location or to read the character at the cursor location when the address changes.
1.4.4.6 Video Output Logic. The video output logic shown in figure 1-44 produces (from the
outputs of refresh memory and the time base generator's line counter) the video signal for
amplification and transmission to the video display unit. The primary character generator produces
seven-bit dot codes for each of the eight scan lines addressed by LINE,A-C,Q. If the graphics
jumper, P9, is not installed, the video output logic suppresses display of the graphics symbols
during scan lines 0 through 7. When a graphic character is presented for display without the graphics
option installed and enabled, the entire character space is intensified (low intensity).
The generators for lines 8 and 9 are installed only for implementing graphics on the 1920-character
displays and produce seven-bit dot codes for scan lines 8 and 9, respectively, of the 7- X 10-dot
character matrix. The latched output of the video output shift register and the outputs of the
video output control latches address the selector to provide the composite video signal to be
driven out to the power/logic pwb. The composite video signal contains a seven-bit dot pattern
for each character of each row of characters to be displayed. Ten scan lines of composite video are
produced and transmitted for each row of characters on the CRT monitor screen (two lines are
blanked when graphics not installed or eight lines are blanked for 960-character displays).
Figure 1-45 illustrates the character space and how it is filled by the three possible matrixes.
Figure 1-46 shows the characters produced within the character space on the CRT screen, including
the graphics characters. Note that other character generators are substituted to produce the unique
symbols for European countries and the Japanese Katakana characters (figure 1-4 7).
1.4.4.7 Alarm Logic. Figure 1-48 shows the alarm logic on the VDT controller. Whenever Beep
Enable is active, AQ goes high to enable the audio logic on the power/logic pwb. NAQ goes low
to enable the timer, then allows the timer to run for approximately 0.25 seconds before clearing
the alarm flip-flop and disabling the audio logic.
1-61
Digital Systems Division