Figure 1-6. Memory Subsystem - HP Integrity rx8620 User's & Service Manual

Introduction
Detailed HP Integrity rx8620 Server Description
Figure 1-6 shows a simplified view of the memory subsystem. It consists of two independent access paths,
each path having its own address bus, control bus, data bus, and DIMMs. In practice, the CC runs the two
paths 180 degrees out of phase with respect to each other to facilitate pipelining in the CC. Address and
control signals are fanned out through register ports to the synchronous dynamic random access memory
(SDRAM) on the DIMMs.
The memory subsystem is composed of four independent quadrants. Each quadrant has its own memory data
bus connecting from the cell controller to the two buffers for the memory quadrant. Each quadrant also has
two memory control buses; one for each buffer.
Figure 1-6 Memory Subsystem
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DIMM
DIMM
Address/
Buffer Controller Buffer
Buffer
DIMM
DIMM
DIMM
DIMM
Address/
Controller
Buffer Buffer
Buffer
DIMM
DIMM
Front Side Bus 1
CPU 2 CPU 3
PDH Riser
Board
Buffer
Buffer
Front Side Bus 0
Cell
Controller
DIMM
DIMM
Address/
Controller Buffer
Buffer
DIMM
DIMM
DIMM
DIMM
Address/
Controller
Buffer
Buffer
DIMM
DIMM
CPU 1 CPU 0
Chapter 1