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PCH 1/9
5
CONSENT STRAP
PESONALITY
STRAP
RESERVED
External pull-up is required. Recommend
ENABLE:LOW
IS ENABLED IF LOW
100K if pulled up to 3.3V or 75K if
(INTERNAL WEAK PU)
PCH HAS NO INTERNAL
pulled up to 1.8V.
TERMINATION
This strap should sample HIGH. There
should NOT be any on-board device
3.3VA_SPI
3.3VA_SPI
driving it to opposite direction during
strap sampling.
GPP_H15
R519
20K_04
R482
R478
PCH
20K_04
20K_04
SPI_IO2
SPI_IO3
PCH
PCH
D
3.3VA
VDD3
BIOS + ME ROM
3.3VA_SPI
R637
R638
SPI_* = 1"~6.5"
0_04
*0_04
U21
SPI_SI_M
PCH
PCH
8
5
VDD
SI
SPI_SO_M
C589
2
SO
R285
SPI_W P#
SPI_CS0#
0.1u_16V_Y5V_04
3
1
WP#
CE#
20K_04
PCH
SPI_SCLK_M
PCH
6
SCK
R272
SPI_HOLD#
C
7
4
HOLD#
VSS
20K_04
PCH
MX25L12873F
PCH
128MB
MX25L12873FM2I-10G
6-04-25128-A72
GD25B127DSIGR
6-04-25127-470
VCCPSPI VOLTAGE SELECT
LOW: 3.3V (DEFAULT)
HIGH: 1.8V
1.8VA_PCH
(INTERNAL WEAK PD)
CNVI_MFUART2_TXD
R151
PCH
*100K_04
R152
PCH
100K_04
GPP_J1
R448
PCH
10K_04
M.2_CNV_BRI_DT_BT_UART0_RTS
R456
PCH
10K_04
M.2_CNV_RGI_DT_BT_UART0_TX
R144
PCH
20K_04
R120
PCH
*100K_04
M.2_CNV_BRI_DT_BT_UART0_RTS
XTAL SELECT-1
LOW: 38.4MHz
HIGH: 24MHz
M.2_CNV_RGI_DT_BT_UART0_TX
M.2 CNVI STRAP
HIGH -> DISABLE
3.3VS
LOW -> ENABLE
B
VCCIO_3P3_PW RGATE
R418
PCH
10K_04
1.8VA_PCH
R645
PCH
20K_04
M.2_CNV_BRI_RSP
49
M.2_CNV_BRI_DT
M.2_CNV_RGI_RSP
R646
PCH
20K_04
49
M.2_CNV_BRI_RSP
49
M.2_CNV_RGI_DT
49
M.2_CNV_RGI_RSP
1.8VA
C759
0.1u_16V_Y5V_04
VCCIO_3P3_PW RGATE
PCH
54
VCCIO_3P3_PW RGATE
C1011
*0.1u_16V_Y5V_04
A
PCH
5
4
3
U175A
BE36
GPP_A11/PME#/SD_VDD2_PWR_EN#
R15
RSVD2
R13
RSVD1
AL37
VSS
AN35
TP
HSPI_MSI
AU41
39
HSPI_MSI
SPI0_MOSI
HSPI_MSO
BA45
39
HSPI_MSO
SPI0_MISO
AY47
39
HSPI_CE#
SPI0_CS0#
AW47
39
HSPI_SCLK
SPI0_CLK
AW48
SPI0_CS1#
SPI_W P#
SPI_IO2
AY48
R493
PCH
33_04
SPI_HOLD#
SPI_IO3
SPI0_IO2
R475
PCH
33_04
BA46
SPI0_IO3
AT40
SPI0_CS2#
BE19
GPP_D1/SPI1_CLK/SBK1_BK1
BF19
GPP_D0/SPI1_CS#/SBK0_BK0
BF18
GPP_D3/SPI1_MOSI/SBK3_BK3
BE18
GPP_D2/SPI1_MISO/SBK2_BK2
BC17
GPP_D22/SPI1_IO3
BD17
GPP_D21/SPI1_IO2
HM370_MP
PCH
HSPI_MSI
R279
PCH
33_04
HSPI_MSO
R287
PCH
33_04
HSPI_CE#
R289
PCH
0_04
HSPI_SCLK
R277
PCH
33_04
R701
*100K_04
PCH
CNVI_WIGIG_DET#
U175M
LOW: CNVi DEVICE
HIGH: Qualcomm WiGig DEVICE
AW13
GPP_G0/SD_CMD
R420
PCH
*1K_04
BE9
39,49
CNVI_W IGIG_DET#
GPP_G1/SD_D0
BF8
GPP_G2/SD_D1
BF9
GPP_G3/SD_D2
BG8
GPP_G4/SD_D3
BE8
R428
PCH
10K_04
3.3VA
GPP_G5/SD_CD#
RB751S-40H
C
A
D26
BD8
39
SW I#
GPP_G6/SD_CLK
AV13
GPP_G7/SD_WP
R467
PCH
*10K_04
3.3VA
AP3
R466
PCH
10K_04
5,34
H_SKTOCC_N
GPP_I11/M2_SKT2_CFG0
PCH
AP2
GPP_I12/M2_SKT2_CFG1
AN4
GPP_I13/M2_SKT2_CFG2
AM7
GPP_I14/M2_SKT2_CFG3
AV6
49
CNVI_GNSS_PA_BLANKING
GPP_J0/CNV_PA_BLANKING
GPP_J1
AY3
56
GPP_J1
GPP_J1/CPU_VCCIO_PWR_GATE#
AR13
GPP_J11/A4WP_PRESENT
AV7
GPP_J10
AW3
GPP_J_2
AT10
GPP_J_3
R451
PCH
33_04
M.2_CNV_BRI_DT_BT_UART0_RTS
AV4
M.2_CNV_BRI_RSP
GPP_J_4_CNV_BRI_DT_UART0_RTSB
AY2
GPP_J5/CNV_BRI_RSP/UART0_RXD
M.2_CNV_RGI_DT_BT_UART0_TX
R134
PCH
33_04
BA4
GPP_J6/CNV_RGI_DT/UART0_TXD
M.2_CNV_RGI_RSP
AV3
GPP_J7/CNV_RGI_RSP/UART0_CTS#
AW2
CNVI_MFUART2_TXD
GPP_J8/CNV_MFUART2_RXD
AU9
GPP_J9/CNV_MFUART2_TXD
HM370_MP
PCH
U31
5
1
VCC
NC
GPP_J1
2
R444
A
10K_04
4
3
PCH
Y
GND
74AUP1G07GW
PCH
9,10,11,12,13,32,33,34,35,38,39,40,41,42,46,47,48,49,51,56,57,58,64
4
3
2
GPP_G_14_GSXDIN:
DMI AC COUPLING FULL VOLTAGE MODE
WHEN SAMPLED LOW
AV29
GPP_B13/PLTRST#
PLT_RST#
29,38
GPP_K_14_GSXDIN:
Y47
GPP_K16/GSXCLK
DMI AC COUPLING FULL VOLTAGE MODE
Y46
GPP_K12/GSXDOUT
WHEN SAMPLED LOW
Y48
GPP_K13/GSXSLOAD
GPP_K_14_GSXDIN
W46
T28
GPP_K14/GSXDIN
AA45
GPP_K15/GSXSRESET#
AL47
GPP_E3/CPU_GP0
AM45
GPP_E7/CPU_GP1
BF32
BT_RF_KILL_R_N
R435
PCH
*0_04
GPP_B3/CPU_GP2
W IFI_RF_KILL_R_N
BC33
R414
PCH
*0_04
GPP_B4/CPU_GP3
AE44
GPP_H18/SML4ALERT#
AJ46
GPP_H17/SML4DATA
AE43
GPP_H16/SML4CLK
GPP_H15
AC47
GPP_H15/SML3ALERT#
AD48
ESPI FLASH SHARING MODE
GPP_H14/SML3DATA
AF47
MASTER ATTACHED FLASH SHARING:LOW
GPP_H13/SML3CLK
GPP_H_12
SLAVE ATTACEHD FLASH SHARING:HIGH
AB47
T82
(INTERNAL WEAK PD)
GPP_H12/SML2ALERT#
AD47
GPP_H11/SML2DATA
AE48
GPP_H10/SML2CLK
BB44
R143
PCH
1M_04
VCC_RTC
INTRUDER#
JOPEN2
*OPEN_10mil-1MM
1 OF 13
PCH
CNV_W R_CLK_DN
BD4
CNV_W R_CLK_DN
49
CNV_WR_CLKN
CNV_W R_CLK_DP
BE3
CNV_W R_CLK_DP
49
CNV_WR_CLKP
CNV_W R_LANE0_DN
BB3
CNV_WR_D0N
CNV_W R_LANE0_DN
49
CNV_W R_LANE0_DP
BB4
CNV_WR_D0P
CNV_W R_LANE0_DP
49
CNV_W R_LANE1_DN
BA3
CNV_W R_LANE1_DN
49
CNV_WR_D1N
BA2
CNV_W R_LANE1_DP
CNV_W R_LANE1_DP
49
CNV_WR_D1P
CNV_W T_CLK_DN
BC5
CNV_WT_CLKN
CNV_W T_CLK_DN
49
CNV_W T_CLK_DP
BB6
CNV_W T_CLK_DP
49
CNV_WT_CLKP
CNV_W T_LANE0_DN
BE6
CNV_W T_LANE0_DN
49
CNV_WT_D0N
CNV_W T_LANE0_DP
BD7
CNV_WT_D0P
CNV_W T_LANE0_DP
49
CNV_W T_LANE1_DN
BG6
CNV_W T_LANE1_DN
49
CNV_WT_D1N
BF6
CNV_W T_LANE1_DP
CNV_W T_LANE1_DP
49
CNV_WT_D1P
CNV_W T_RCOMP
BA1
R443
CNV_WT_RCOMP
MPHY_RCOMPN
B12
R542
PCH
100_1%_04
PCIE_RCOMPN
MPHY_RCOMPP
A13
PCIE_RCOMPP
BE5
SD3_RCOMP_1P8
R122
PCH
200_1%_04
SD_RCOMP_1P8
SD3_RCOMP_3P3
BE4
R119
PCH
200_1%_04
SD_RCOMP_3P3
BD1
GPPJ_RCOMP_1P81
BE1
GPPJ_RCOMP_1P82
BE2
GPPJ_RCOMP_1P8
R441
PCH
200_1%_04
GPPJ_RCOMP_1P83
Y35
RSVD2
Y36
RSVD3
BC1
RSVD1
AL35
TP
13 OF 13
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
36
1.8VA_PCH
36,54,56
1.05VA
Title
Title
Title
[30] PCH A,M/13-SPI/SMBUS
[30] PCH A,M/13-SPI/SMBUS
[30] PCH A,M/13-SPI/SMBUS
33,36,53,54
1.8VA
33,36
VCC_RTC
5,33,34,36,38,53,54
3.3VA
Size
Size
Size
Document Number
Document Number
Document Number
6-71-P95E0-D02A
6-71-P95E0-D02A
6-71-P95E0-D02A
3.3VS
A3
A3
A3
P950ER
P950ER
P950ER
5,27,31,33,36,38,39,42,47,48,49,51,52,53,54,55,56,57,63,64
VDD3
Date:
Date:
Date:
Monday, February 12, 2018
Monday, February 12, 2018
Monday, February 12, 2018
2
Schematic Diagrams
1
D
BT_EN
39,49
W LAN_EN
39,49
Sheet 30 of 72
PCH 1/9
C
B
PCH
150_1%_04
A
R e v
R e v
R e v
D02A
D02A
D02A
Sheet
Sheet
Sheet
30
30
30
o f
o f
o f
72
72
72
1
PCH 1/9 B - 31
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