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Schematic Diagrams
DDR4 CHA SO-DIMM_0
Channel A SO-DIMM 0[RAM1]
D
PLACE THE CAP WITHIN 200 MILS FROM THE SODIMM
10,33
PLACE THE CAP CLOSE TO SODIMM
Sheet 9 of 72
DDR4 CHA SO-
DIMM_0
C
C313
10u_6.3V_X5R_06
2DIMM
C304
B
10u_6.3V_X5R_06
2DIMM
VDDQ
C319
10u_6.3V_X5R_06
2DIMM
VDDQ
A
C348
10u_6.3V_X5R_04
2DIMM
B - 10 DDR4 CHA SO-DIMM_0
5
4
4
M_A_DIM0_CK_DDR0_DP
4
M_A_DIM0_CK_DDR0_DN
4
M_A_DIM0_CK_DDR1_DP
4
M_A_DIM0_CK_DDR1_DN
4
M_A_DIM0_CKE0
4
M_A_DIM0_CKE1
4
M_A_DIM0_CS0_N
4
M_A_DIM0_CS1_N
DDR4_DRAMRST#
DDR4_DRAMRST#
4
M_A_DIM0_ODT0
4
M_A_DIM0_ODT1
4
M_A_BG0
4
M_A_BG1
4
M_A_BA0
4
M_A_BA1
4
4
4
4
4
DDR_VREFCA_CHA_DIMM
4
4
4
4
C442
C458
4
4
M_A_A10_AP
0.1u_16V_X7R_04
*2.2u_6.3V_X5R_04
4
2DIMM
2DIMM
4
4
4
M_A_A14_W E_N
VDDQ
4
M_A_A15_CAS_N
4
M_A_A16_RAS_N
R197
4
M_A_ACT_N
240_1%_04
4
DDR0_A_PARITY
2DIMM
4
DDR0_A_ALERT_N
32
DIMM0_CHA_EVENT_N
CHA_DIMM0=000
10,33
SMB_DATA_R
2.5V
10,33
SMB_CLK_R
CHA_DIMM1=001
CHB_DIMM0=010
C745
CHB_DIMM1=011
1u_6.3V_X5R_04
2DIMM
VTT_MEM
C308
1u_6.3V_X5R_04
2DIMM
C402
C323
C425
C361
C356
C339
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
2DIMM
2DIMM
2DIMM
2DIMM
2DIMM
2DIMM
C340
1u_6.3V_X5R_04
2DIMM
5
4
3
STD TYPE
H=4mm
J_DIMMA_1A
M_A_DQ5
137
8
CK0_T
DQ0
M_A_DQ0
139
7
CK0_C
DQ1
M_A_DQ2
138
20
CK1_T
DQ2
140
21
M_A_DQ3
CK1_C
DQ3
M_A_DQ1
4
DQ4
M_A_DQ4
109
3
CKE0
DQ5
M_A_DQ6
110
16
CKE1
DQ6
17
M_A_DQ7
DQ7
M_A_DQ8
149
28
S0*
DQ8
M_A_DQ12
157
29
S1*
DQ9
M_A_DQ14
41
DQ10
155
42
M_A_DQ11
ODT0
DQ11
M_A_DQ9
161
24
ODT1
DQ12
M_A_DQ13
25
DQ13
M_A_DQ10
115
38
BG0
DQ14
113
37
M_A_DQ15
BG1
DQ15
M_A_DQ17
150
50
BA0
DQ16
M_A_DQ20
145
49
BA1
DQ17
M_A_DQ23
62
DQ18
144
63
M_A_DQ18
M_A_A0
A0
DQ19
M_A_DQ16
133
46
M_A_A1
A1
DQ20
M_A_DQ21
132
45
M_A_A2
A2
DQ21
M_A_DQ19
131
58
M_A_A3
A3
DQ22
128
59
M_A_DQ22
M_A_A4
A4
DQ23
M_A_DQ25
126
70
M_A_A5
A5
DQ24
M_A_DQ28
127
71
M_A_A6
A6
DQ25
M_A_DQ30
122
83
M_A_A7
A7
DQ26
125
84
M_A_DQ31
M_A_A8
A8
DQ27
M_A_DQ24
121
66
M_A_A9
A9
DQ28
M_A_DQ29
146
67
A10_AP
DQ29
M_A_DQ27
120
79
M_A_A11
A11
DQ30
119
80
M_A_DQ26
M_A_A12
A12
DQ31
M_A_DQ32
158
174
M_A_A13
A13
DQ32
M_A_DQ37
151
173
A14_WE*
DQ33
M_A_DQ39
156
187
A15_CAS*
DQ34
152
186
M_A_DQ34
A16_RAS*
DQ35
M_A_DQ36
170
DQ36
M_A_DQ33
169
DQ37
M_A_DQ38
114
183
ACT*
DQ38
182
M_A_DQ35
DQ39
M_A_DQ41
143
195
PARITY
DQ40
M_A_DQ45
116
194
ALERT*
DQ41
M_A_DQ46
134
207
EVENT*
DQ42
DDR4_DRAMRST#
108
208
M_A_DQ42
RESET*
DQ43
M_A_DQ44
191
DQ44
DDR_VREFCA_CHA_DIMM
M_A_DQ40
164
190
VREFCA
DQ45
M_A_DQ43
203
DQ46
254
204
M_A_DQ47
SDA
DQ47
M_A_DQ49
253
216
SCL
DQ48
M_A_DQ52
215
000
DQ49
M_A_DQ55
166
228
SA2
DQ50
260
229
M_A_DQ51
SA1
DQ51
M_A_DQ50
256
211
SA0
DQ52
M_A_DQ48
212
DQ53
M_A_DQ53
224
DQ54
225
M_A_DQ54
DQ55
M_A_DQ61
92
237
CB0_NC
DQ56
M_A_DQ60
91
236
CB1_NC
DQ57
M_A_DQ58
101
249
CB2_NC
DQ58
105
250
M_A_DQ63
CB3_NC
DQ59
M_A_DQ56
88
232
CB4_NC
DQ60
M_A_DQ57
87
233
CB5_NC
DQ61
M_A_DQ62
100
245
CB6_NC
DQ62
104
246
M_A_DQ59
CB7_NC
DQ63
M_A_DQS0
12
13
VDDQ
DM0*/DBI0*
DQS0_T
M_A_DQS1
33
34
DM1*/DBI1*
DQS1_T
54
55
M_A_DQS2
DM2*/DBI2*
DQS2_T
M_A_DQS3
75
76
DM3*/DBI3*
DQS3_T
M_A_DQS4
178
179
DM4*/DBI4*
DQS4_T
M_A_DQS5
199
200
DM5*/DBI5*
DQS5_T
220
221
M_A_DQS6
DM6*/DBI6*
DQS6_T
M_A_DQS7
241
242
DM7*/DBI7*
DQS7_T
96
97
DM8*/DBI8*
DQS8_T
11
M_A_DQS#0
DQS0_C
M_A_DQS#1
32
DQS1_C
M_A_DQS#2
53
DQS2_C
M_A_DQS#3
74
DQS3_C
177
M_A_DQS#4
DQS4_C
M_A_DQS#5
198
DQS5_C
M_A_DQS#6
219
DQS6_C
M_A_DQS#7
240
DQS7_C
95
DQS8_C
162
S2*/C0
165
S3*/C1
D4AS0-26001-1P40
2DIMM
6-86-24260-002
4
7,10,33,54,57
10,57
10,57
10,11,12,13,30,32,33,34,35,38,39,40,41,42,46,47,48,49,51,56,57,58,64
3
2
1
VDDQ
VTT_MEM
J_DIMMA_1B
13A
2A
163
258
2.5V
VDD19
VTT
160
M_A_DQ[63:0]
4
VDD18
159
VDD17
154
259
VDD16
VPP2
153
257
VDD15
VPP1
148
VDD14
147
VDD13
142
VDD12
141
VDD11
136
255
VDD10
VDDSPD
135
VDD9
130
VDD8
129
C755
VDD7
124
VDD6
123
0.1u_16V_X7R_04
VDD5
118
2DIMM
VDD4
117
VDD3
112
VDD2
111
VDD1
GND1
MT1
GND2
MT2
PLACE NEAR TO PIN
251
252
VSS
VSS
247
248
VSS
VSS
243
244
VSS
VSS
239
238
VSS
VSS
235
234
VSS
VSS
231
230
VSS
VSS
227
226
VSS
VSS
223
222
VSS
VSS
217
218
VSS
VSS
213
214
VSS
VSS
209
210
VSS
VSS
205
206
VSS
VSS
201
202
VSS
VSS
197
196
VSS
VSS
193
192
VSS
VSS
189
188
VSS
VSS
185
184
VSS
VSS
181
180
VSS
VSS
175
176
VSS
VSS
171
172
VSS
VSS
167
168
VSS
VSS
107
106
VSS
VSS
103
102
VSS
VSS
99
98
VSS
VSS
93
94
VSS
VSS
89
90
VSS
VSS
85
86
VSS
VSS
81
82
VSS
VSS
77
78
VSS
VSS
73
72
VSS
VSS
69
68
VSS
VSS
65
64
VSS
VSS
61
60
VSS
VSS
57
56
VSS
VSS
51
52
VSS
VSS
47
48
VSS
VSS
43
44
VSS
VSS
39
40
VSS
VSS
35
36
VSS
VSS
31
30
VSS
VSS
27
26
VSS
VSS
23
22
VSS
VSS
19
18
M_A_DQS[3:0]
4
VSS
VSS
15
14
VSS
VSS
9
10
VSS
VSS
5
6
VSS
VSS
1
2
M_A_DQS[7:4]
4
VSS
VSS
D4AS0-26001-1P40
2DIMM
M_A_DQS#[3:0]
4
VDDQ
M_A_DQS#[7:4]
4
R211
D I M M
C329
1K_1%_04
10u_6.3V_X5R_06
2DIMM
DDR_VREFCA_CHA_DIMM
2DIMM
C457
R210
0.1u_16V_X7R_04
1K_1%_04
2DIMM
2DIMM
R216
1.8_1%_04
2DIMM
DIMM_CA_CPU_VREF_A
C456
0.022u_25V_X7R_04
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
2DIMM
R209
24.9_1%_04
Title
Title
Title
[09] DDR4 CHA SO-DIMM_0
[09] DDR4 CHA SO-DIMM_0
[09] DDR4 CHA SO-DIMM_0
2DIMM
VDDQ
Size
Size
Size
Document Number
Document Number
Document Number
VTT_MEM
6-71-P95E0-D02A
6-71-P95E0-D02A
6-71-P95E0-D02A
A3
A3
A3
P950ER
P950ER
P950ER
2.5V
3.3VS
Date:
Date:
Date:
Monday, February 12, 2018
Monday, February 12, 2018
Monday, February 12, 2018
Sheet
Sheet
Sheet
2
1
3.3VS
D
C306
2.2u_6.3V_X5R_04
2DIMM
C
B
A
R e v
R e v
R e v
D02A
D02A
D02A
9
9
9
o f
o f
o f
72
72
72
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