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Register Name
ESM_SOC_MODE_ CFG
RTC_CTRL_2
PFSM_DELAY_REG_1
PFSM_DELAY_REG_2
PFSM_DELAY_REG_3
PFSM_DELAY_REG_4
GENERAL_REG_0
GENERAL_REG_1
5.11 Interface Settings
These settings detail the default interface, interface configurations, and device addresses. These settings
cannot be changed after device startup.
Register Name
SERIAL_IF_CONFIG
I2C1_ID_REG
I2C2_ID_REG
5.12 Watchdog Settings
These settings detail the default watchdog addresses. These settings can be changed though I
Register Name
WD_LONGWIN_CFG
WD_THR_CFG
SLVUCD4 – NOVEMBER 2022
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Table 5-10. Miscellaneous NVM Settings (continued)
Field Name
ESM_SOC_EN
XTAL_EN
LP_STANDBY_SEL
FAST_BIST
STARTUP_DEST
XTAL_SEL
PFSM_DELAY1
PFSM_DELAY2
PFSM_DELAY3
PFSM_DELAY4
EN_OVP
VSYS_DEAD_LOCK_EN
PFSM_ERR_RESET_DIS
DIS_UVLO_OVP_RESET
FAST_BOOT_BIST
VMON_ABIST_EN
ABIST_ERROR_MASK
REG_CRC_EN
FAST_VCCA_OVP
Table 5-11. Interface NVM Settings
Field Name
I2C_SPI_SEL
I2C1_SPI_CRC_EN
I2C2_CRC_EN
I2C1_ID
I2C2_ID
Table 5-12. Watchdog NVM Settings
Field Name
WD_LONGWIN
WD_EN
User Guide for Powering Jacinto
Copyright © 2022 Texas Instruments Incorporated
TPS65941515-Q1
Value
Description
0x0
ESM_SoC disabled.
0x1
Crystal oscillator is enabled
0x1
Low Power Standby state is used as
STANDBY state (LDOINT is disabled)
0x0
Logic and analog BIST is run at BOOT BIST
0x3
ACTIVE
0x1
9 pF
0x58
0x58
0x9d
0x9d
0x0
0x0
0x0
0x0
0x1
OVP Enabled
0x1
Turn off VCCA with external FET in case of
VCCA OVP
0x0
PFSM_ERR causes reset to logic
0x0
UVLO/OVP cause reset to logic
0x0
LBIST is run during boot BIST
0x1
VMON ABIST enabled
0x0
ABIST errors not masked
0x1
Register CRC enabled
0x0
Slow; 4us deglitch filter enabled
TPS65941515-Q1
Value
Description
0x0
I2C
0x0
CRC disabled
0x0
CRC disabled
0x48
0x48
0x12
0x12
TPS65941515-Q1
Value
Description
0xff
0xff
0x1
Watchdog enabled.
TM
7 J7200 DRA821 with Single TPS6594-Q1
Static NVM Settings
2
C after startup.
23
PMIC, PDN-2A
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