Texas Instruments TPS65941213-Q1 User Manual page 32

Pre-Configurable Finite State Machine (PFSM) Settings
Recovery Count
Threshold
RECOVERY
FSM
PFSM
MCU Power Error
Immediate Shutdown
Orderly Shutdown
From any PFSM State
Warm Reset triggered by
ESM SOC or WatchDog Error
Valid On Request
STARTUP_DEST[1:0] = 10b
Pwr SOC Error
DDR
Warm Reset triggered by
MCU SOC or WatchDog Error
Figure 6-1. Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions
When the PMICs transition from the FSM to the PFSM, several initialization instructions are performed to disable
the residual voltage checks on both the BUCK and LDO regulators, set the FIRST_STARTUP_DONE bit and
32 Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Jacinto™ 7 J721E, PDN-0C
INIT
INIT Complete
No Errors
No Residual Voltage
SAFE BOOT BIST
Error
Valid On Request
STARTUP_DEST[1:0] = 11b
SOC Power Error
B
C or
D
B
C or
D
Copyright © 2022 Texas Instruments Incorporated
Valid Wake
Request
BOOT BIST
BOOT BIST
Success
LP_STANDBY_SEL
=1
STANDBY
Off Request
ACTIVE
A or WKUP1 or
Valid On Request
STARTUP_DEST[1:0] = 11b
MCU Only
STARTUP_DEST[1:0] = 11b
DDR
B or WKUP2 or
Valid On Request
STARTUP_DEST[1:0] = 10b
Retention
DDR
Trigger NSLEEP2
A 1
B 1
C 0
D 0
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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LP_STANDBY
OFF Request
OFF Request
A or WKUP1 or
Valid On Request
NSLEEP1
1
0
1
0
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