Texas Instruments TPS65941213-Q1 User Manual page 45

www.ti.com
Resource PMIC
nRSTOUT_SOC TPS65941213-Q1
GPIO3 TPS65941111-Q1
BUCK5 TPS65941111-Q1
LDO3 TPS65941111-Q1
BUCK1234 TPS65941111-Q1
LDO3 TPS65941213-Q1
BUCK123 TPS65941213-Q1
LDO4 TPS65941111-Q1
BUCK5 TPS65941213-Q1
LDO1 TPS65941213-Q1
LDO1 TPS65941111-Q1
LDO2 TPS65941111-Q1
GPIO11 TPS65941111-Q1
GPIO9 TPS65941213-Q1
LDO4 TPS65941213-Q1
LDO2 TPS65941213-Q1
BUCK4 TPS65941213-Q1
BUCK3 Monitor TPS65941213-Q1
nRSTOUT TPS65941213-Q1
Figure 6-10. TO_MCU Sequence with I2C_7 low in both PMICs
The last instructions of the TO_MCU sequence also perform writes to the MISC_CTRL and
ENABLE_DRV_STAT registers after the delay defined in the PFSM_DELAY_REG_1.
// TPS65941213
SREG_READ_REG ADDR=0xCD REG=R1
DELAY_SREG R1
// Clear SPMI_LPM_EN and FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xE7
// Set NRSTOUT (MCU_PORZ)
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x01 MASK=0xFE
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
Submit Document Feedback
Delay Diagram
Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Copyright © 2022 Texas Instruments Incorporated
Pre-Configurable Finite State Machine (PFSM) Settings
Total Delay
0 us
500 us
500 us
500 us
2500 us
2500 us
2500 us
3000 us
3000 us
3000 us
3500 us
3500 us
3500 us
3500 us
5200 us
7200 us
7200 us
7200 us
16200 us
Jacinto™ 7 J721E, PDN-0C
Rail Name
H_SOC_PORz_1V8
EN_VDDR
VDD_RAM_0V85
VDD_IO_1V8
VDD_CORE_0V8
VDD_DLL_0V8
VDD_CPU(AVS)
VDA_PLL_1V8
VDD_PHY_1V8
VDD1_DDR_1V8
VDD_SD_DV
VDD_USB_3V3
EN_3V3IO_LDSW
EN_MCU3V3IO_LDSW
VDA_MCU_1V8
VDD_MCUIO_1V8
VDD_MCU_0V85
mVDD_MCUIO_3V3
H_MCU_PORz_1V8
45