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(6)
After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings.
(7)
The GPIO2 triggers are referring to GPIO2 on the TPS65941111.
(8)
When in the ACTIVE mode, the ON Request to MCU ONLY trigger cannot be accessed while other higher priority triggers, like
NSLEEP1=NSLEEP2=HIGH, are still active.
(9)
These triggers can originate from either the TPS65941213 or the TPS65941111. All other triggers except for the GPIO2 triggers
originate from the TPS65941213.
(10) Trigger IDs 23 and 24 are not available until the NSLEEP bits are masked: NSLEEP2_MASK=NSLEEP1_MASK=1.
(11) Trigger IDs 3, 25, and 26 are enabled and activated by the power sequences. These triggers are used to manage the transition
between the PFSM and the FSM.
6.3 Power Sequences
6.3.1 TO_SAFE_SEVERE and TO_SAFE
The TO_SAFE_SEVERE and TO_SAFE are distinct sequences which occur when transition to the SAFE state.
Both sequences shut down all rails without delay. The TO_SAFE_SEVERE sequence immediately ceases
BUCK switching and enables the pulldown resistors of the BUCKs and LDOs. This is to prevent any damage
of the PMICs in case of over voltage on VCCA or thermal shutdown. The timing is illustrated in
TO_SAFE sequence does not reset the BUCK regulators until after the regulators are turned off.
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
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Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Copyright © 2022 Texas Instruments Incorporated
Pre-Configurable Finite State Machine (PFSM) Settings
Jacinto™ 7 J721E, PDN-0C
Figure
6-2. The
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