Samsung S3C9454B User Manual page 155

BASIC TIMER and TIMER 0
MUX
1/4096
1/1024
X
DIV
IN
1/128
R
Bit 0
R
1/4096
1/256
DIV
X
IN
NOTE: During a power-on Reset operation, the CPU is idle during the required oscillation stabilization interval
(until bit 4 the basic timer counter is set).
10-10
Bit 1
Bits 3, 2
Clear
8-Bit Up Counter
(BTCNT, Read-Only)
MUX
Bits 7, 6
MUX
1/8
1
8-Bit Comparator
Figure 10-7. Basic Timer and Timer 0 Block Diagram
RESET or
STOP
Basic Timer Control Register
(Write '1010xxxxB' to disable.)
Data Bus
When BTCNT.4 is set after
releasing from RESET or STOP
mode, CPU clock starts.
Data Bus
T0CNT (D0H)
(Read-Only)
T0DATA Buffer
T0DATA (D1H)
(Read/Write)
Data Bus
OVF
Clear Bit 3
Bit 1
Match
Bit 0
P2.0
P2CONL.1-.0
Bit 3
Match Signal
Basic Timer Control Register
Timer 0 Control Register
S3C9454B/F9454B
RESET
IRQ0