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Programming the Board
6.3.4
Position Acquisition with Hardware Support
In this mode, the board offers the user support in processing the registers. The zero-marking-pulse
input of the respective channel plays an important role. An arriving zero marking pulse triggers the
following events on the board.
•
The current counter status is stored in the zero-marking-pulse buffer where it can then be read.
•
Counter write protection is set so that the zero-marking-pulse buffer cannot be overwritten by an
event. (It cannot be overwritten by a zero-marking-pulse signal or SW strobe.) The counter itself
is also protected from write accesses or "clear" events (see chapter 6.3.10). Write protection can
be reset with the "cancel counter write protection" command (see chapter 6.3.7).
•
The following status bits are set for each of the two counting channels.
Status Bits, Counting Channel 0
SCH0 (status register 0, bit 3)
REF0 (status register 0, bit 0)
Q0 (status register 1, bit 6)
INT (interrupt register, counting
channel 0)
The meaning of these signals is described in chapter 6.4.
The "one-time" and "cyclic" modes
When hardware support is activated, you can choose between "one-time" and "cyclic" mode. With
one-time mode (control register 0, bit 3 = "0" for counting channel 0 or bit 1 = "0" for counting channel
1) the one-time counter is set when a zero marking pulse arrives. This prevents (also with counter
write protection disabled) additional zero-marking pulses from being registered and overwriting the
zero-marking-pulse buffer.The zero-marking-pulse input is enabled again with the "enable one-time
counter" command for the particular counting channel.
Only zero-marking-pulse signals are disabled while the one-time counter is set. Write accesses to the
counter and commands (SW strobe, SW clear, etc.) can continue to be performed if counter write
protection is canceled.
The one-time counter is not used during cyclic mode and is also not set.
Note:
Hysteresis can be used for the zero-marking-pulse logic (see chapter 6.3.11).
32
Status Bits, Counting Channel 1
SCH1 (status register 0, bit 2)
REF1 (status register 0, bit 1)
Q1 (status register 1, bit 7)
INT (interrupt register, counting
channel 1)
SMP16-SFT251
©Siemens AG 2003, All Rights Reserved
(4)J31069-D2090-U001-A1-7618
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