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SMP16-SFT251
6.3
Function Description
6.3.1
Reading the Counter Status
The counter states cannot be read directly from the counter. Before the counter status can be read, it
must be saved in a register. The "zero-marking-pulse-buffer" registers and the universal registers are
used for this purpose. See chapter 6.1.
The counter status is transferred to the zero-marking-pulse buffer when a zero-marking pulse arrives
or an SW-strobe occurs. Depending on the status of the BG_Mode bit, the buffer can then be read
with byte or word-accesses (see chapter 6.1). The read sequence is unimportant.
Note:
SW strobe will only work with operating mode "position acquisition with hardware support" when write
protection of the particular channel is disabled (see chapter 6.3.4).
Chapters 6.3.8 and 6.3.9 explain how the universal registers function.
6.3.2
Loading the Counters
Both counters can be preloaded with start values. A counter-load register is assigned to each counter
for this purpose. The data that will be loaded to the counter are intermediately stored in this register
until the next loading procedure occurs. Actual loading of the counter differs depending on the status
of the BG_Mode board mode bit (see also chapter 6.4.2).
BG_Mode = "0"
In this case, the counter can only be addressed with 8-bit accesses as described in chapter 6.1. Each
byte is loaded directly to the counter. The order in which the bytes are written to the counter is
unimportant.
Note:
In this board mode, the counters should only be loaded when no counting signals are queued on the
inputs. Otherwise, the counter states may no longer be consistent.
BG_Mode = "1"
In this board mode, ASBIC channel 0 can only be addressed with 16-bit accesses (see chapter 6.1).
The data must be written to the address of the counters in the following order: high word first (counter
bits 16 to 31) and low word second (counter bits 0 to 15). The high word is first stored intermediately in
the counter-load register. Not until the low word is loaded to the counter is the counter synchronously
loaded with all 32 bits. This type of counter loading ensures that all four counter bytes arrive at the
counter at the same time and that all four bytes are available simultaneously for the counting
procedure. This makes it possible to load the counter synchronously even during running operation.
Note:
Loading the counters will only work with operating mode "position acquisition with hardware support"
when write protection of the particular channel is disabled (see chap. 6.3.4).
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Programming the Board
29
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