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SMP16-SFT251
Note:
Hysteresis can be used for the comparator function (see chapter 6.3.11).
6.3.10
The Clear Functions
Various mechanisms can be used to reset the counter of a channel. The CLR_MD0 control bits in
control register 1 or the CLR_MD1 control bits in control register 2 can be used to select whether the
arrival of a reset event is to set the counter to "00000000h" ("set counter to zero") or to a certain value
which is stored intermediately ("reload for clear") in the counter load register (see chapter 6.3.2).
The following table provides information on how to trigger a reset function and the modes which can
be set.
Trigger
Activation
Arriving zero-
Bit 6 (channel 0) or bit 7
marking pulse of
(channel 1) on the parallel
the shaft encoder
output port of the ASBIC
Counter equal to
Bit 9 (CR1n_CLR) in
control register 1 or 2
universal register
UREG_10
(channel 0)
or UREG_11
(channel 1)
Special signal
Bit 8 (ZS3n_CLR) in
ZS30 (channel 0)
control register 1 or 2
or
ZS31 (channel 1)
SW clear
Always active
(channel 0 or 1)
SW reload
Always active
(channel 0 or 1)
1)
n = channel number (0 or 1)
©Siemens AG 2003, All Rights Reserved
(4)J31069-D2090-U001-A1-7618
Available Function Mode
"Set Counter to Zero"
Bit 10 (CLR_MD) = "0"
in control register 1 or 2
Bit 10 (CLR_MD) = "0"
1)
in control register 1 or 2
Bit 10 (CLR_MD) = "0"
1)
in control register 1 or 2
Sets the counter to
"00000000"
-------
Programming the Board
"Reload for Clear"
Bit 10 (CLR_MD) = "1"
in control register 1 or 2
Bit 10 (CLR_MD) = "1"
in control register 1 or 2
Bit 10 (CLR_MD) = "1"
in control register 1 or 2
-------
Loads the counter with the
contents of the counter load
register
41
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