Mvme162Fx Mc68040 Indivisible Cycles - Motorola MVME162FX Programmer's Reference Manual

Software Support Considerations
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has been granted. Because we have found in the past that some
VME systems can become very busy, we recommend this time-out
be set at a large value, such as 32 msec.
Once the VMEbus has been granted, a third timer takes over. This
is the global VMEbus timer. This timer starts when a transfer
actually begins (DS0 or DS1 goes active) and ends when that
transfer completes (DS0 or DS1 goes inactive). This time should be
longer than any expected legitimate transfer time on the bus. We
normally set it to 256 sec. This timer can also be disabled for debug
purposes. Before an MVME162FX access to another MVME162FX
can complete, however, the VMEchip2 on the accessed
MVME162FX must decode a slave access and request the local bus
of the second MVME162FX. When the local bus is granted (any
in-process onboard transfers have completed) then the local bus
timer of the accessed MVME162FX starts. Normally, this is also set
to 256 µsec. When the memory has the data available, a transfer
acknowledge signal (TA) is given. This translates into a DTACK
signal on the VMEbus which is then translated into a TA signal to
the first requesting processor, and the transfer is complete. If the
VMEbus global timer expires on a legitimate transfer, the VMEbus
to local bus controller in the VMEchip2 may become confused and
the VMEchip2 may misbehave. Therefore the bus timers values
must be set correctly. The correct settings depend on the system
configuration.

MVME162FX MC68040 Indivisible Cycles

The MC68040 performs operations that require indivisible
read-modify-write (RMW) memory accesses. These RMW
sequences occur when the MMU modifies table entries or when the
MPU executes a TAS, CAS, or CAS2 instruction. TAS cycles are
always single-address RMW operations, while the CAS, CAS2, and
MMU operations can be multiple-address RMW cycles. The
VMEbus does not support multiple-address RMW cycles and there
is no defined protocol for supporting multiple-address RMW cycles
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