Local Dram Parity Error; Vmechip2; Bus Error Processing - Motorola MVME162FX Programmer's Reference Manual

Board Description and Memory Maps
1

Local DRAM Parity Error

VMEchip2

Bus Error Processing

1-40
software accesses a nonexistent device within the VMEbus range,
incorrect configuration information causes the VMEchip2 to
incorrectly access a device on the VMEbus (such as driving
LWORD* low to a 16-bit board), a hardware error occurs on the
VMEbus, or a VMEbus slave reports an access error (such as parity
error).
The present MVME162FX models do not contain parity
Note
DRAM.
When parity checking is enabled, the current bus master receives a
bus error if it is accessing the local DRAM and a parity error occurs.
An 8- or 16-bit write to the LCSR in the VMEchip2 causes a local
BERR*.
Because different conditions can cause bus error exceptions, the
software must be able to distinguish the source. To aid in this,
status registers are provided for every local bus master. The next
section describes the various causes of bus error and the associated
status registers.
Generally, the bus error handler can interrogate the status bits and
proceed with the result. However, an interrupt can happen during
the execution of the bus error handler (before an instruction can
write to the status register to raise the interrupt mask). If the
interrupt service routine causes a second bus error, the status that
indicates the source of the first bus error may be lost. The software
must be written to deal with this.