Dma Control And Status Register Set Definition - Motorola MVME162FX Programmer's Reference Manual

IP2 Chipming Model
4
DMA Control and Status Register Set Definition
4-34
The following are legal contexts for DMA channel configurations.
Note that configuration rules for DMA controllers for IP_a and IP_b
are defined. The same relationships exist for IP_c and IP_d.
If IP_a data bus is 8 or 16 bits, there are not any restrictions
placed on IP_b.
If IP_a data bus is 32 bits and the ADMA mode is selected,
then the DMA controller associated with IP_b cannot be used.
If A_CH1 bit is set in the DMA controller register associated
with IP_b and both channel A and B operate in the SDMA
mode, then the DMA channels associated with IP_a and IP_b
can both be used if the data width for channel A and B are set
equal. This case allows the DMA channel that normally re-
sponds to IP_b-DMAreq_0 pin to respond to IP_a-DMAreq_1
pin. This enables full duplex communications operation at
IP_a.
The four sets of DMA controller CSRs are almost identical in
functionality. Each register set is grouped as DMACa, DMACb,
DMACc, and DMACd. These register sets are shown pictorially in
the CSR register summary section. Only one register set is defined
except that the offset is noted for the four possible values. Refer to
the definitions of bit 1 of the DMA Control Register 1 for a
description of how the register sets are associated with the physical
DMA request from the Industry Packs.