MC2 Chip
ADR/SIZ
3
BIT
NAME
OPER
RESET
Bus Clock Register
ADR/SIZ
BIT
NAME
OPER
RESET
3-40
Tick Timer 4 Counter
31
The Bus Clock Register should be programmed with the
hexadecimal value of the operating clock frequency in MHz (i.e.,
$20 for 32 MHz). The MC2 chip uses the value programmed in this
register to control the refresh timer so that the DRAMs are
refreshed every 15.6 microseconds. After powerup, this register is
initialized to $10 (for 16 MHz).
31
30
29
BCK5
R/W
R/W
0 P
0 P
0 P
BCK5-BCK0 The refresh rate is defined by the following
equation:
where BCK is the value programmed in the Bus
Clock Register, and BUS CLOCK is the MC68xx040
bus clock frequency.
$FFF4203C (32 bits)
. . .
Tick Timer 4 Counter
R/W
X
$FFF42040 (8 bits)
28
27
BCK4
BCK3
R/W
1 P
0 P
Refresh Rate = BCK/BUS CLOCK * 16
0
26
25
24
BCK2
BCK1
BCK0
0 P
0 P
0 P