Programming The Vmechip2 Dma Controller - Motorola MVME162FX Programmer's Reference Manual

VMEchip2

Programming the VMEchip2 DMA Controller

2
2-52
2VMEchip2
2LCSR Programming Model
This section includes programming information on the DMA
controller, VMEbus interrupter, MPU status register, and local bus
to VMEbus requester register.
The VMEchip2 features a local bus -VMEbus DMA controller
(DMAC). The DMAC has two modes of operation: command
chaining, and direct. In the direct mode, the local bus address, the
VMEbus address, the byte count, and the control register of the
DMAC are programmed and the DMAC is enabled. The DMAC
transfers data, as programmed, until the byte count is zero or an
error is detected. When the DMAC stops, the status bits in the
DMAC status register are set and an interrupt is sent to the local bus
interrupter. If the DMAC interrupt is enabled in the local bus
interrupter, the local bus is interrupted. The time on and time off
timers should be programmed to control the VMEbus bandwidth
used by the DMAC.
A maximum of 4GB of data may be transferred with one DMAC
command. Larger transfers can be accomplished using the
command chaining mode. In the command chaining mode, a
singly-linked list of commands is built in local memory and the
table address register in the DMAC is programmed with the
starting address of the list of commands. The DMAC control
register is programmed and the DMAC is enabled. The DMAC
executes commands from the list until all commands are executed
or an error is detected. When the DMAC stops, the status bits are
set in the DMAC status register and an interrupt is sent to the local
bus interrupter. If the DMAC interrupt is enabled in the local bus
interrupter, the local bus is interrupted. When the DMAC finishes
processing a command in the list, and interrupts are enabled for
that command, the DMAC sends an interrupt to the local bus
interrupter. If the DMAC interrupt is enabled in the local bus
interrupter, the local bus is interrupted.
The DMAC control is divided into two registers. The first register is
only accessible by the processor. The second register can be loaded
by the processor in the direct mode and by the DMAC in the
command chaining mode.