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Field Name
D1GRPH_Y_START
Primary graphic Y start coordinate relative to the desktop coordinates.
Field Name
D1GRPH_X_END
Primary graphic X end coordinate relative to the desktop coordinates.
Field Name
D1GRPH_Y_END
Primary graphic Y end coordinate relative to the desktop coordinates.
Field Name
D1GRPH_MODE_UPDATE_PENDING (R)
D1GRPH_MODE_UPDATE_TAKEN (R)
© 2007 Advanced Micro Devices, Inc.
Proprietary
D1GRPH_Y_START - RW - 32 bits - DISPDEC:0x6130
Bits
Default
12:0
0x0
D1GRPH_X_END - RW - 32 bits - DISPDEC:0x6134
Bits
Default
13:0
0x0
D1GRPH_Y_END - RW - 32 bits - DISPDEC:0x6138
Bits
Default
13:0
0x0
D1GRPH_UPDATE - RW - 32 bits - DISPDEC:0x6144
Bits
Default
0
0x0
1
0x0
Description
Primary graphic Y start coordinate relative to the desktop coordi-
nates.
Description
Primary graphic X end coordinate relative to the desktop coordinates.
It is exclusive and the maximum value is 8K
Description
Primary graphic Y end coordinate relative to the desktop coordinates.
It is exclusive and the maximum value is 8K
Description
Primary graphic mode register update pending control. It is set to 1
after a host write to graphics mode register. It is cleared after double
buffering is done.
This signal is only visible through register.
The graphics surface register includes:
D1GRPH_DEPTH
D1GRPH_FORMAT
D1GRPH_SWAP_RB
D1GRPH_LUT_SEL
D1GRPH_LUT_10BIT_BYPASS_EN
D1GRPH_ENABLE
D1GRPH_X_START
D1GRPH_Y_START
D1GRPH_X_END
D1GRPH_Y_END
The mode register double buffering can only occur at vertical retrace.
The double buffering occurs when
D1GRPH_MODE_UPDATE_PENDING = 1 and
D1GRPH_UPDATE_LOCK = 0 and V_UPDATE = 1.
If CRTC1 is disabled, the registers will be updated instantly.
0=No update pending
1=Update pending
Primary graphics update taken status for mode registers. It is set to 1
when double buffering occurs and cleared when V_UPDATE = 0.
M56 Register Reference Manual
Display Controller Registers
2-201
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