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GENERICB_SEL
Field Name
DC_PAD_EXTERN_SIG_SEL
Select for PAD_EXTERN_SIGNAL
Field Name
HSYNCA_OUTPUT_SEL
HSYNCB_OUTPUT_SEL
Control output of external reference clocks
© 2007 Advanced Micro Devices, Inc.
Proprietary
11:8
0x0
DC_PAD_EXTERN_SIG - RW - 32 bits - DISPDEC:0x7DCC
Bits
Default
3:0
0x0
DC_REF_CLK_CNTL - RW - 32 bits - DISPDEC:0x7DD4
Bits
Default
1:0
0x0
9:8
0x0
Select signal for GENERICB pad
0=DACA Stereosync
1=DACB Stereosync
2=DACA PIXCLK
3=DACB PIXCLK
4=DVOA CTL3
5=P1 PLLCLK
6=P2 PLLCLK
7=DVOA Stereosync
8=DACA Field Number
9=DACB Field Number
10=GENERICB test debug clock from DCCG
11=SYNCEN
12=GENERICA test debug clock from SCG
13=Reserved
14=Reserved
15=Reserved
Description
Select pin PAD_EXTERN_SIGNAL is connected to
0=PAD_EXTERN_SIGNAL is connected to HSYNCA pin
1=PAD_EXTERN_SIGNAL is connected to VSYNCA pin
2=PAD_EXTERN_SIGNAL is connected to HSYNCB pin
3=PAD_EXTERN_SIGNAL is connected to VSYNCB pin
4=PAD_EXTERN_SIGNAL is connected to GENERICA pin
5=PAD_EXTERN_SIGNAL is connected to GENERICB pin
6=PAD_EXTERN_SIGNAL is connected to GENERICC pin
7=PAD_EXTERN_SIGNAL is connected to HPD1 pin
8=PAD_EXTERN_SIGNAL is connected to HPD2 pin
9=PAD_EXTERN_SIGNAL is connected to DDC1CLK pin
10=PAD_EXTERN_SIGNAL is connected to DDC1DATA pin
11=PAD_EXTERN_SIGNAL is connected to DDC2CLK pin
12=PAD_EXTERN_SIGNAL is connected to DDC2DATA pin
13=PAD_EXTERN_SIGNAL is connected to VHAD(0) pin
14=PAD_EXTERN_SIGNAL is connected to VHAD(1) pin
15=PAD_EXTERN_SIGNAL is connected to VPHCTL pin
Description
0=Reference Clock Output disabled
1=PPLL1 Reference Clock Output
2=PPLL2 Reference Clock Output
3=Reserved
0=Reference Clock Output disabled
1=PPLL1 Reference Clock Output
2=PPLL2 Reference Clock Output
3=Reserved
M56 Register Reference Manual
Display Output Registers
2-325
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