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-SMEMR (O) -MEMR(I/O)
These signals instruct the memory devices to drive data onto the data
bus. "-SMEMR" is active only when the memory decode is within the
low 1Mb of memory space. "-MEMR" is active on all memory read
cycles. "-MEMR" may be driven by any microprocessor or DMA control-
ler in the system. "-SMEMR" is derived from "MEMR" and the decode
of the low 1 Mb of memory. When a microprocessor on the I/O channel
wishes to drive "-MEMR", it must have the address lines valid on the
bus for one system clock period before driving "-MEMR" active. Both
signals are active LOW.
-SMEMW (O) -MEMW (i/O)
These signals instruct the memory devices to store the data present
on the data bus. "-SMEMW" is active only when the memory decode
is within the low 1Mb of the memory space. "-MEMW" is active on all
memory read cycle. "-MEMW" may be driven by any microprocessor
or DMA controller in the system. "SMEMW" is derived from "-MEMW"
and the decode of the low 1 Mb of memory. When a microprocessor on
the l/O channel wishes to drive "-MEMW", it must have the address
lines valid on the bus for one system clock period before driving
"-MEMW" active. Both signals are active low.
DRQ0-DRQ3 and DRQ5-DRQ7 (I)
DMA Requests 0 through 3 and 5 through 7 are asynchronous channel
requests used by peripheral devices and the I/O channel micreproces-
sors to gain DMA service (or control of the system). They are
prioritized, with "DRQ0" having the highest priority and "DRQ7" having
the lowest. A request is generated by bringing a DRQ line to an active
level. A DRQ line must be held high until the corresponding "DMA
Request Acknowledge" (DACK) line goes active. "DRQ0" through
"DRQ3" will perform El-bit DMA transfers; "DRQ5" through "DRQ7" will
perform 16-bit transfers. "DRQ4" is used on the system board and is
not available on the I/O channel.
-DACK0 to -DACK3 and -DACK5 to -DACK7 (0)
-DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA
requests (DRQ0 through DRQ7). They are active low.
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Chapter 6: Appendix
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