Dma Channel - DTK Apex 386/33 User Manual

DMA Channels
Your mainboard supports up to seven DMA channels. Two 8237 DMA
controllers are in the VLSI 82C100 chip. Each 8237 has four DMA
channels. DMA controller 1 has channel 0 through channel 3 and DMA
controller 2 contains channel 4 through channel 7. Channel 4 of
controller 2 is used to cascade the four channels of the controller 1,
namely, channel 0 through channel 3, to the microprocessor. DMA
channel assignments are listed below:
CTR 1
CH0
CH1
CH2
CH3
Table 6-10: DMA Channels
The channels of DMA Controller 1 support data transfers between 8-bit
I/O adapters and 8-bit or 16-bit system memory, and the channels of
DMA Controller 2 are used for 16-bit data transfers between 16-bit I/O
adapters and 16-bit system memory.
I/O Channel
This section describes the I/O channel, lists the pin assignments,
describes each I/O channel signal line and gives the I/O address map.
The I/O channel has the following features:
I/O address space from 100h to 3FFh
Selection of data accesses (8-bit or 16-bit)
16MB memory address space
11 levels of interrupt
7 DMA channels
Open-bus structure (allowing multiple microprocessors to
share system resources, including system memory)
Spare CH4
SDLC CH5
Diskette CH6
Spare CH7
CTR 2
Cascade for CTRL 1
Spare
Spare
Spare
Chapter 6: Appendix
33