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The direct-mapped cache organization diagram above shows how
data contained in cache are accessed.
For example, if the 80386 requests data at the address FFFFF9h in the
main memory, the procedure is as follows:
Cache Updating - Write-Back System
In a write-back system, the tag field of each block in the cache includes
a bit called the ALTERED bit. The bit is set if the block has been written
with new data and therefore contains data that is more recent than the
corresponding data in the main memory. Before writing any block in the
cache, the cache-controlled logic checks the altered bit. If it is set, the
cache controlled logic writes the block to the main memory before
loading new data into the cache.
The write-back system is faster than the write-through system because
the number of times an altered block must be copied into the main
memory is usually less than the number of write accesses.
26
Chapter 6: Appendix
The cache-controlled logic determines the cache location
from the 14 least significant bits of the index field (FFF8h).
The cache controlled logic compares the tag field (FFh) with
the tag stored at location FFF8h in the tag RAM.
If the tag matches, the processor reads the second byte of
the 4-byte sub-block from the data in the cache RAM.
If the tag does not match, the cache logic fetches the 4-byte
sub-block at address FFFFF8h in the main memory and
loads it into location FFF8h of the cache RAM, replacing the
current sub-block. The logic also changes the tag stored at
locations FFF8h to FFh. The processor then reads the
second byte of the new four-byte sub-block.
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