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LA17 Through LA23 (I/O)
These signals (unlatched) are used to address memory and I/O
devices within the system. They give the system up to 16 MB of
addressability. These signals are valid when "BALE" is high. LA17
through LA23 are not latched during microprocessor cycles and there-
fore do not stay valid for the whole cycle. Their purpose is to generate
memory decodes for 1 wait-state memory cycles. These decodes
should be latched by I/O adapters on the falling edge of "BALE". These
signals also may be driven by other microprocessors or DMA control-
lers that reside on the l/O channel.
CLK (0)
This is the 8.25MHz system clock with a cycle time of 121
nanoseconds. The clock has a 50% duty cycle. This signal should only
be used for synchronization. It is not intended for uses requiring a fixed
frequency.
RESET DRV (0)
"Reset drive" is used to reset or initialize system logic at power-up time
or during a low line voltage outage. This signal is active high.
SD0 Through SD15 (I/O)
These signals provide bus bits 0 though 15 for the microprocessor,
memory, and l/O devices. DO is the least-significant bit and D15 is the
most significant bit.. All 8-bit devices on the I/O channel should use DO
through D7 for communications to the microprocessor. The 16-bit
devices will use DO through D15. To support 6-bit devices, the data on
D8 through D15 will be gated to DO through D7 during 8-bit transfers
to these devices: 16-bit microprocessor transfers to 8-bit devices will
be converted to two 8-bit transfers.
BALE (0) (Buffered)
"Address latch enable" is provided by the 82288 Bus Controller and is
used on the system board to latch valid addresses and memory
decodes from the microprocessor. It is available to the I/O channel as
an indicator of a valid microprocessor or DMA address (when used with
"AEN"). Microprocessor addresses SA0 through SA19 are latched with
the falling edge of "BALE" "BALE" is forced high during DMA cycles.
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Chapter 6: Appendix
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