Denon DRA-800H Service Manual page 42

DIGITAL_OSD : IC732
BY25Q32BSSIG (except : E2)
BY25Q64ASSIG (only E2)
Top View
/CS VCC
1 8
SO
2 7 /HOLD
SOP8 208mil
SCLK
/WP
6
3
VSS SI
5
4
SN74CBT3251
1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER
SCDS019L − MAY 1995 − REVISED JANUARY 2004
SN74CBT3251PWR (DIGITAL_OSD : IC733)
(each multiplexer/demultiplexer)
INPUTS
OE S2
L L
L L
L L
L L
L H
L H
L H
L H
H X
logic diagram (positive logic)
Block diagram
5
A
7
OE
11
S0
10
S1
9
S2
2
POST OFFICE BOX 655303
Pin Name I/O Description
/CS I Chip Select
Serial Output for single bit data Instructions. IO1 for Dual or Quad
SO (IO1) I/O
Instructions.
Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.
/WP (IO2) I/O The signal has an internal pull-up resistor and may be left unconnected
in the host system if not used for Quad Instructions.
VSS Ground
Serial Input for single bit data Instructions. IO0 for Dual or Quad
SI (IO0) I/O
Instructions.
SCLK I Serial Clock
Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in
/HOLD (IO3) I/O Quad-I/O mode. The signal has an internal pull-up resistor and may be
left unconnected in the host system if not used for Quad Instructions.
VCC Core and I/O Power Supply
FUNCTION TABLE
FUNCTION FUNCTION
S1 S0
L L A port = B1 port
L H A port = B2 port
H L A port = B3 port
H H A port = B4 port
L L A port = B5 port
L H A port = B6 port
H L A port = B7 port
H H A port = B8 port
X X Disconnect
4
B1
3
B2
2
B3
1
B4
15
B5
14
B6
13
B7
12
B8
•
DALLAS, TEXAS 75265
TPS563201 (DIGITAL_DIGITAL SUPPLY : IC741, IC742, IC743, IC744)
Terminal Functions
PIN
NUMBER
NAME
(I/O)
Ground pin Source terminal of low-side power NFET as well as the ground ter-
GND 1(-)
minal for controller circuit. Connect sensitive VFB to this GND at a single point.
SW 2(O) Switch node connection between high-side NFET and low-side NFET.
VIN 3(I) Input voltage supply pin. The drain terminal of high-side power NFET.
Converter feedback input. Connect to output voltage with feedback resistor
VFB 4(I)
divider.
EN 5(I) Enable input control. Active high and must be pulled up to enable the device.
Supply input for the high-side NFET gate drive circuit. Connect 0.1 μ F capaci-
VBST 6(O)
tor between VBST and SW pins.
Block diagram
EN 5
V +
UVP
UVP

+
OVP
V 
OVP
VFB 4
Voltage Ref
Reference
SS
Soft Start
t
ON
One-Shot
TSD
OCL
Threshold
42
DDC Package
6-Pin SOT
Top View
GND 1 6 VBST
SW 2 5 EN
VIN 3 4 VFB
DESCRIPTION
3 VIN
Hiccup
VREG5
Control Logic
Regulator
UVLO
6 VBST
 PWM
+
+
HS
XCON 2 SW
VREG5
LS

OCL
1 GND
+
+
ZC
