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Intel® Server System M50FCP1UR System Integration and Service Guide
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two Hex Nibble values are combined to
create a single ACh POST Progress Code.
D.1 Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
MRC
Upper Nibble
Progress
Code
8h
4h
(Hex)
73
0
1
7E
0
1
B0
1
0
B1
1
0
B2
1
0
B3
1
0
B4
1
0
B5
1
0
B6
1
0
B7
1
0
0
0
0
3
0
0
4
0
0
11
0
0
77
0
1
B8
1
0
B9
1
0
BA
1
0
BB
1
0
BC
1
0
BE
1
0
BF
1
0
Should a major memory initialization error occur, preventing the system from booting with data integrity, a
beep code is generated, the MRC displays a fatal error code on the diagnostic LEDs, and a system halt
command is executed. Fatal MRC error halts do not change the state of the system status LED and they do
not get logged as SEL events.
Note: Fatal MRC errors display POST error codes that may be the same as BIOS POST progress codes
displayed later in the POST process. The fatal MRC codes can be distinguished from the BIOS POST progress
codes by the accompanying memory failure beep code of three long beeps as identified in
100
Table 9. MRC Progress Codes
Lower Nibble
2h
1h
8h
4h
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Table 10
lists all MRC fatal errors that are displayed to the diagnostic LEDs.
2h
1h
1
1
NVRAM sync.
1
0
MRC internal sync.
0
0
Detect DIMM population
0
1
Set DDR5 frequency
1
0
Gather remaining SPD data
1
1
Program registers on the memory controller level
0
0
Evaluate RAS modes and save rank information
0
1
Program registers on the channel level
1
0
Perform the JEDEC defined initialization sequence
1
1
Train DDR5 ranks
0
0
Train DDR5 channels: Receive enable training
1
1
Train DDR5 channels: Read DQ/DQS training
0
0
Train DDR5 channels: Write DQ/DQS training
0
1
Train DDR5 channels: End of channel training.
1
1
Train DDR5 channels: Write leveling training.
0
0
Initialize CLTT/OLTT
0
1
Hardware memory test and initialization
1
0
Execute software memory initialization
1
1
Program memory map and interleaving
0
0
Program RAS configuration
1
0
Execute BSSA RMT
1
1
MRC is done
Description
Table 13.
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