Early Post Memory Initialization Mrc Diagnostic Codes; Table 49. Mrc Progress Codes - Intel R1000WF Technical Product Specification

Intel® Server System R1000WF Product Family Technical Product Specification
B.1.

Early POST Memory Initialization MRC Diagnostic Codes

Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Upper Nibble
Post Code
(Hex) 8h 4h
B0 1 0
B1 1 0
B2 1 0
B3 1 0
B4 1 0
B5 1 0
B6 1 0
B7 1 0
01 0 0
02 0 0
03 0 0
04 0 0
05 0 0
B8 1 0
B9 1 0
BA 1 0
BB 1 0
BC 1 0
BF 1 0
Should a major memory initialization error occur, preventing the system from booting with data integrity, a
beep code is generated, the MRC displays a fatal error code on the diagnostic LEDs, and a system halt
command is executed. Fatal MRC error halts do not change the state of the system status LED and they do
not get logged as SEL events. Table 50 lists all MRC fatal errors that are displayed to the diagnostic LEDs.
Note: Fatal MRC errors display POST error codes that may be the same as BIOS POST progress codes
displayed later in the POST process. The fatal MRC codes can be distinguished from the BIOS POST progress
codes by the accompanying memory failure beep code of three long beeps as identified in Table 53.
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Table 49. MRC progress codes

Lower Nibble
2h 1h 8h 4h 2h
1 1 0 0 0
1 1 0 0 0
1 1 0 0 1
1 1 0 0 1
1 1 0 1 0
1 1 0 1 0
1 1 0 1 1
1 1 0 1 1
0 0 0 0 0
0 0 0 0 1
0 0 0 0 1
0 0 0 1 0
0 0 0 1 0
1 1 1 0 0
1 1 1 0 0
1 1 1 0 1
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
1h
0 Detect DIMM population
1 Set DDR4 frequency
0 Gather remaining SPD data
1 Program registers on the memory controller level
0 Evaluate RAS modes and save rank information
1 Program registers on the channel level
0 Perform the JEDEC defined initialization sequence
1 Train DDR4 ranks
1 Train DDR4 ranks
0 Train DDR4 ranks – Read DQ/DQS training
1 Train DDR4 ranks – Receive enable training
0 Train DDR4 ranks – Write leveling training
1 Train DDR4 ranks – DDR channel training done
0 Initialize CLTT/OLTT
1 Hardware memory test and init
0 Execute software memory init
1 Program memory map and interleaving
0 Program RAS configuration
1 MRC is done
Description