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5.8 Control Registers
MISC Vector Table Address Low Register
Register name
Bit
MSCTTBRL
15–8 TTBR[15:8]
7–0 TTBR[7:0]
Bits 15–0 TTBR[15:0]
These bits set the vector table base address (16 low-order bits).
MISC Vector Table Address High Register
Register name
Bit
MSCTTBRH
15–8 –
7–0 TTBR[23:16]
Bits 15–8 Reserved
Bits 7–0
TTBR[23:16]
These bits set the vector table base address (eight high-order bits).
ITC Interrupt Level Setup Register x
Register name
Bit
ITCLVx
15–11 –
10–8 ILVy
7–3 –
2–0 ILVy
Bits 15–11 Reserved
Bits 7–3
Reserved
Bits 10–8 ILVy
[2:0]
1
Bits 2–0
ILVy
[2:0]
0
These bits set the interrupt level of each interrupt.
ITCLVx.ILVy[2:0] bits
The following shows the ITCLVx register configuration in this IC.
Register name
Bit
ITCLV0
15–11 –
(ITC Interrupt Level
10–8 ILV1[2:0]
Setup Register 0)
7–3 –
2–0 ILV0[2:0]
ITCLV1
15–11 –
(ITC Interrupt Level
10–8 ILV3[2:0]
Setup Register 1)
7–0 –
ITCLV2
15–11 –
(ITC Interrupt Level
10–8 ILV5[2:0]
Setup Register 2)
7–0 –
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name
Initial
0x80
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
[2:0]
0x0
1
0x00
[2:0]
0x0
0
(y
= 2x +1)
1
(y
= 2x)
0
Table 5.8.1 Interrupt Level and Priority Settings
Interrupt level
0x7
0x6
· · ·
0x1
0x0
Table 5.8.2 List of ITCLVx Registers
Bit name
Initial
0x00
0x0
0x00
0x0
0x00
0x0
0x00
0x00
0x0
0x00
Seiko Epson Corporation
5 INTERRUPT CONTROLLER (ITC)
Reset
R/W
H0
R/WP –
H0
R
Reset
R/W
–
R
–
H0
R/WP
Reset
R/W
–
R
–
H0
R/W
–
R
H0
R/W
Priority
7
High
6
↑
· · ·
1
↓
0
Low
Reset
R/W
–
R
–
H0
R/W
Port interrupt (ILVPPORT)
–
R
–
H0
R/W
Supply voltage detector interrupt
(ILVSVD3)
–
R
–
H0
R/W
Clock generator interrupt (ILVCLG)
–
R
–
–
R
–
H0
R/W
16-bit timer Ch.0 interrupt (ILVT16_0)
–
R
–
Remarks
Remarks
Remarks
Remarks
5-5
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