Input/Output Pins; Clock Sources - Epson S1C17M12 Technical Manual

CLG
IOSCEN
oscillator
OSC3EN
OSC3
X'tal3/Ceramic3
oscillator
OSC4
EXOSCEN
EXOSC EXOSC
clock input
FOUTEN
FOUT
FOUTDIV[2:0]

2.3.2 Input/Output Pins

Table 2.3.2.1 lists the CLG pins.
Pin name I/O*
OSC3 A
OSC4 A
EXOSC I
FOUT O
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the "I/O Ports" chapter.

2.3.3 Clock Sources

IOSC oscillator circuit
The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1
shows the configuration of the IOSC oscillator circuit.
The IOSC oscillator circuit output clock IOSCCLK is used as SYSCLK at booting. For the oscillation charac-
teristics, refer to "IOSC oscillator circuit characteristics" in the "Electrical Characteristics" chapter.
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
IOSC
IOSCCLK
Divider
circuit
OSC3
OSC3CLK
Divider
circuit
EXOSCCLK
circuit
FOUT
output
circuit
Figure 2.3.1.1 CLG Configuration
Table 2.3.2.1 List of CLG Pins
Initial status*
– OSC3 oscillator circuit input
– OSC3 oscillator circuit output
I EXOSC clock input
O (L) FOUT clock output
IOSC oscillator circuit
IOSCEN
Oscillation
Clock
stabilization
oscillator
waiting circuit
IOSCSTAIE
Interrupt
control circuit
Figure 2.3.3.1 IOSC Oscillator Circuit Configuration
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
System
Clock
clock
selector
controller
SLEEP, WAKE-UP
Clock
selector
Clock
selector
Function
* Indicates the status when the pin is configured for CLG.
IOSCCLK
IOSCSTAIF
Interrupt
controller
SYSCLK
To CPU and bus
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
2-5