Table of Contents
Advertisement
6 I/O PORTS (PPORT)
Bits 15–8 PxPDPU[7:0]
These bits select either the pull-up resistor or the pull-down resistor when using a resistor built into
the port.
1 (R/W): Pull-up resistor
0 (R/W): Pull-down resistor
The selected pull-up/down resistor is enabled when the PxRCTL.PxRENy bit = 1.
Bits 7–0
PxREN[7:0]
These bits enable/disable the port pull-up/down control.
1 (R/W): Enable (The built-in pull-up/down resistor is used.)
0 (R/W): Disable (No pull-up/down control is performed.)
Enabling this function pulls up or down the port when output is disabled (PxIOEN.PxOENy bit = 0).
When output is enabled (PxIOEN.PxOENy bit = 1), the PxRCTL.PxRENy bit setting is ineffective re-
gardless of how the PxIOEN.PxIENy bit is set and the port is not pulled up/down.
These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function.
Px Port Interrupt Flag Register
Register name
Bit
PxINTF
15–8 –
7–0 PxIF[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0
PxIF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
Px Port Interrupt Control Register
Register name
Bit
PxINTCTL
15–8 PxEDGE[7:0]
7–0 PxIE[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxEDGE[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
Bits 7–0
PxIE[7:0]
These bits enable port input interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared
before enabling interrupts.
Px Port Chattering Filter Enable Register
Register name
Bit
PxCHATEN
15–8 –
7–0 PxCHATEN[7:0]
*1: The bit configuration differs depending on the port group.
6-8
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
–
H0
R/W
Reset
R/W
–
R
–
H0
R/W
S1C17M12/M13 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.2)
Advertisement
Table of Contents
