Mmcm And Pll Port Descriptions - Xilinx 7 Series User Manual

Chapter 3: Clock Management Tile
Table 3-6: PLL Ports (Cont'd)
Pin Name
DI[15:0]
DWE
DEN
DCLK
(1)
CLKOUT[0:5] Output
CLKFBOUT Output
LOCKED Output
DO[15:0] Output
DRDY Output

MMCM and PLL Port Descriptions

CLKIN1 – Primary Reference Clock Input
CLKIN1 can be driven by SRCC or MRCC I/O directly within the same clock region, SRCC
or MRCC I/O through the CMT backbone in a vertically adjacent clock region, BUFG,
BUFR, BUFH, interconnect (not recommended), or directly by a high-speed serial
transceiver. When the clock input is coming from another CMT block for cascading CMT
functions, only CLKOUT[0:3] can be used.
CLKIN2 – Secondary Clock Input
CLKIN2 is a secondary clock input that is used to dynamically switch the MMCM/PLL
reference clock. CLKIN2 can be driven by SRCC or MRCC I/O directly within the same
clock region, SRCC or MRCC I/O through the CMT backbone in a vertically adjacent clock
region, BUFG, BUFR, BUFH, interconnect (not recommended), or directly by a high-speed
serial transceiver.
CLKFBIN – Feedback Clock Input
Must be connected either directly to the CLKFBOUT for internal feedback or IBUFG
(through a clock-capable pin for external deskew), BUFG, BUFH, or interconnect (not
recommended). For external clock alignment, the feedback path clock buffer type should
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I/O
The dynamic reconfiguration data input (DI) bus provides reconfiguration data.
Input
When not used, all bits must be set to zero.
The dynamic reconfiguration write enable (DWE) input pin provides the write
Input enable control signal to write the DI data into the DADDR address. When not used,
it must be tied Low.
The dynamic reconfiguration enable (DEN) provides the enable control signal to
Input access the dynamic reconfiguration feature. When the dynamic reconfiguration
feature is not used, DEN must be tied Low.
Input The DCLK signal is the reference clock for the dynamic reconfiguration port.
User configurable clock outputs (0 through 5) that can be divided versions of the
VCO phase outputs (user controllable) from 1 (bypassed) to 128. The input clock and
output clocks are phase aligned.
Dedicated PLL feedback output.
An output from the PLL that indicates when the PLL has achieved phase alignment
within a predefined window and frequency matching within a predefined PPM
range. The PLL automatically locks after power on, no extra reset is required.
LOCKED will be deasserted if the input clock stops or the phase alignment is
violated (e.g., input clock phase shift). The PLL must be reset after LOCKED is
deasserted.
The dynamic reconfiguration output bus provides PLL data output when using
dynamic reconfiguration.
The dynamic reconfiguration ready output (DRDY) provides the response to the
DEN signal for the PLLs dynamic reconfiguration feature.
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Pin Description
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012