Vita 57.1 Fmc Hpc Connector J1; Multi-Gigabit Transceiver Data Port 0; Multi-Gigabit Transceiver Data Port 1 - Xilinx XM104 User Manual

FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
Downloaded from Elcodis.com electronic components distributor

1. VITA 57.1 FMC HPC Connector J1

This connector interfaces to the board containing the Xilinx FPGA and mating FMC
connector. The XM104 uses Samtec FMC HPC connector part number ASP-134488-01. The
XM104 connector mates with an FMC connector.
See Xilinx board user guides and schematics for a description of features provided by HPC
interfaces contained on the board, including power supply specifications, FPGA banking
connectivity, and FPGA pin assignments.
• For ML605 LPC and HPC interfaces, see
See the VITA57.1 Specification at
FMC.

2. Multi-Gigabit Transceiver Data Port 0

Board FPGA multi-gigabit transceiver Data Port 0 signals are wired to SMA connectors on
the XM104. Data Port 0 connections between the XM104 FMC HPC connector and four
SMA connectors are defined in
Table 1-3: FPGA Multi-Gigabit Transceiver Data Port 0 Connectivity
FMC HPC Connector
J1 Pin
C6
C7
C2
C3
Notes:
1. AC coupled using a series 0.1 uF capacitor

3 Multi-Gigabit Transceiver Data Port 1

Board FPGA multi-gigabit transceiver Data Port 1 signals are wired to SMA connectors on
the XM104. Data Port 1 connections between the XM104 FMC HPC connector and four
SMA connectors are defined in
Table 1-4: FPGA Multi-Gigabit Transceiver Data Port 1 Connectivity
FMC HPC Connector J1
Pin
A2
A3
A22
A23
Notes:
1. AC coupled using a series 0.1 uF capacitor
UG534
www.vita.com/fmc.html
Table 1-3.
Signal Name
(1)
DP0_M2C_P
(1)
DP0_M2C_N
DP0_C2M_P
DP0_C2M_N
Table 1-4.
Signal Name
(1)
DP1_M2C_P
(1)
DP1_M2C_N
DP1_C2M_P
DP1_C2M_N
www.xilinx.com
Board Technical Description
ML605 Hardware User Guide
for additional information on
SMA Connector
J3
J4
J5
J6
SMA Connector
J7
J8
J9
J10
13