Revision History - Xilinx 7 Series User Manual

Revision History

The following table shows the revision history for this document.
Date Version
03/01/11 1.0
03/28/11 1.1
05/31/11 1.2
10/27/11 1.3
02/16/12 1.4
www.BDTIC.com/XILINX
UG472 (v1.5) July 13, 2012
Initial Xilinx release.
Updated disclaimer and copyright on
and Figure 2-2. Revised the discussion in
Table 1-1 and Figure 2-1. Revised some of the
the description under Figure
Updated Figure 2-20. Updated the
description in Table 2-8. Revised
Primitive section including
Buffer—BUFH, BUFHCE section. Moved
Updated the MMCMs and PLLs
Integer Divide section including
regions in CLKOUT[0:6] – Output
Moved and revised VHDL and Verilog Templates and the Clocking
Added Appendix A, Multi-Region
Added section on 7 Series FPGAs Clocking Differences from Previous FPGA
Generations.
Updated Figure 2-2. Clarified discussion in
removing Table 1-1: Migration of devices in the same package with different top/bottom
alignments. Redrew Figure
Updated description of CLKOUT[0:6]
Feedback Clock Status, page
updating Figure 3-10. Added more information to the
Equation 3-5.
Revised Figure A-6 and Figure
Connectivity Variations per Clock
Moved 7 Series FPGAs Clocking Differences from Previous FPGA
Clock Buffer Selection Considerations. Clarified description in
Added another note after
Clocking section.
Updated Figure 3-6, page
Fractional Divide in the MMCM, page
Dynamic Mode in the MMCM, page
CLKOUT[0:6] – Output Clocks, page
Revised description of STARTUP_WAIT, page
page 74. Updated CLKOUT[0]_DIVIDE_F
Clock Network Deskew, page 68
Updated Table B-1 and added
Replaced "clocking backbone" with "clock backbone" and "clocking region" with "clock
region" throughout.
Added Chapter 1, Clocking
from Previous FPGA Generations
from Appendix B. Updated
XC7A50T from Table 1-2.
Added Clock-Capable Inputs. Updated
Primitive. Updated Horizontal Clock Buffer—BUFH,
before Figure 2-27.
www.xilinx.com
Revision
page 2. Updated
Clock-Capable Inputs
Global Clock Buffers
2-17. Updated the I/O Clock Buffer—BUFIO
Regional Clock Buffer—BUFR
Figure 2-23. Added the BUFMRCE to the
Figure 2-25. Added BUFHCE to the
Clock Gating for Power
section. Revised the
Figure 3-4. Revised the discussion around adjacent
Clocks. Updated the examples after
Clocking.
Clock-Capable Inputs
2-4, Figure 2-16, Figure 2-18, and
in Table 3-5. Updated
79. Clarified the MMCM/PLL relationship including
A-7. Added Appendix B, Clocking Resources and
Region.
Figure 2-22, page 51. Added the
69. Clarified descriptions in
69, Interpolated Fine Phase Shift in Fixed or
71, Determine the Input Frequency, page
78, and Reference Clock Switching, page
81. Updated
allowed values in
adding Figure 3-12, page
Table B-2.
Overview, containing 7 Series FPGAs Clocking Differences
from Chapter 2 and
Table 1-1. Removed XC7A8, XC7A15, XC7A30T, and
Global Clocking
7 Series FPGAs Clocking Resources User Guide
Clocking Architecture Overview
including adding
descriptions. Revised
section.
section. Updated the
BUFMR
Horizontal Clock
Savings.
Frequency Synthesis Only Using
Equation
Wizard.
section including
Figure 2-22.
CLKFBSTOPPED –
Phase Shift section, including
Generations. Added
Clock-Capable Inputs.
Stacked Silicon Interconnect
Frequency Synthesis Using
72,
87.
RST description in Table 3-5,
Table 3-7, page 79. Updated
88.
Summary of Clock Connectivity
Resources, including BUFMR
BUFHCE. Updated paragraph
3-11.