Chapter 1: Clocking Overview; Clocking Architecture Overview; Clock Routing Resources Overview - Xilinx 7 Series User Manual

Clocking Overview
This chapter provides an overview of the 7 series FPGAs clocking, a comparison between
7 series FPGAs clocking and previous FPGA generations, and a summary of clocking
connectivity within the 7 series FPGAs. For detailed information on usage of 7 series
FPGAs clocking resources, see
Management

Clocking Architecture Overview

The 7 series FPGAs clocking resources manage complex and simple clocking requirements
with dedicated global and regional I/O and clocking resources. The Clock Management
Tiles (CMT) provide clock frequency synthesis, deskew, and jitter filtering functionality.
Non-clock resources, such as local routing, are not recommended when designing for clock
functions.
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For clocking purposes, each 7 series device is divided into clock regions.
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Clock Routing Resources Overview

Each I/O bank contains Clock Capable Input pins to bring user clocks onto the
7 series FPGA clock routing resources. In conjunction with dedicated clock buffers, the
Clock Capable Input bring user clocks onto:
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Tile.
I/O columns on the left and right sides of devices contain clock-capable input (Clock
Capable Input) pins to bring in user clocks to clocking resources.
Global clock trees allow clocking of synchronous elements across the device.
I/O and regional clock trees allow clocking of up to three vertically adjacent clock
regions.
CMTs, each containing one mixed-mode clock manager (MMCM) and one
phase-locked loop (PLL), reside in the CMT column next to the I/O column.
The number of clock regions varies with device size, from eight clock regions in the
smallest device to 24 clock regions in the largest one.
A clock region includes all synchronous elements (CLB, I/O, GT, DSP, block RAM,
CMT, etc.) in an area spanning 50 CLBs and one I/O bank (50 I/Os), with a horizontal
clock row (HROW) in its center.
Each clock region spans 25 CLBs up and 25 CLBs down from the HROW, and
horizontally across each side of the device.
Global clock lines in the same top/bottom half of the device
I/O clocks lines within the same I/O bank and vertically adjacent I/O banks
Regional clock lines within the same clock region and vertically adjacent clock regions
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Chapter 2, Clock Routing Resources
Chapter 1
and Chapter 3, Clock
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