System Consideration; Module Descriptions - Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual

System Consideration

Buffer Requirements
The FIFO depth is selectable via the GUI when the core is generated. The buffering
requirement for the asynchronous FIFO depends mainly on the relative frequency of the
AXI4-Stream clock (aclk) to the video clock (vid_in_clk) frequency, and the line
standard being used.
If the frequency of the AXI4-Stream clock (Faclk) is equal to or greater than the frequency of
the Video input pixel clock (Fvclk), only the minimum buffer size (32 locations) is required.
This assumes that the cores connected downstream of the Video In to AXI4-Stream core can
sink data at the full video rate. e.g. The downstream core can accept data in a virtually
continuous stream with gaps occurring only following EOL, and each line consecutively with
line gaps only preceding SOF. In this scenario, the FIFO will go empty after the EOL on each
line.
If Faclk is less than Fvclk, additional buffering is required. The FIFO must store enough
pixels to supply pixels continuously throughout the active line. Additionally, due to phasing
requirements, the horizontal active period on the output will overlap the effective blanking
period of pixels coming in from the AXI4-Stream bus. This means that the input FIFO must
also be large enough to provide output pixels continuously during this time.
For AXI4-Stream clock frequencies above the line average but below that of video input
pixel clock, the minimum FIFO initial fill level must be:
FIFO depth min. = 32+ Active Pixels * Fvclk/Faclk
If the downstream processing core accepts data at a lower rate than the AXI4-Stream clock,
Additional buffering is required in an amount sufficient to prevent the FIFO from
overflowing during the course of a frame.

Module Descriptions

Figure 1-1 shows a block diagram of the Video In to AXI4-Stream core. The video
connections are on the left, and the AXI4-Stream interface is on the right. There are two
main blocks, the data formatter and the stream coupler. The stream coupler contains an
Asynchronous FIFO. These two blocks are described in detail below:
Video In to AXI4-Stream
PG043 April 24, 2012
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System Consideration
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