Feature Descriptions - Xilinx KC705 User Manual

The KC705 board block diagram is shown in
available for download from The KC705 Evaluation Kit Product Page:
Caution!
ESD prevention measures when handling the board
X-Ref Target - Figure 1-1
1 GB DDR3 Memory
Differential Clock
GTX SMA Clock
XADC Header
User Switches,
Buttons, and LEDs
HDMI Video
Interface
1 KB EEPROM (I 2 C)
I 2 C Bus Switch
Config and Flash Addr

Feature Descriptions

Figure 1-2
is described in the sections that follow.
Note:
board.
KC705 Evaluation Board
UG810 (v1.4) July 18, 2013
• Linear BPI Flash memory
• Quad SPI
• USB JTAG configuration port
• Platform cable header JTAG configuration port
www.xilinx.com/kc705
The KC705 board can be damaged by electrostatic discharge (ESD). Follow standard
FMC Connectors
(SODIMM) (HPC/LPC)
Kintex-7 FPGA
XC7K325T-2FFG900C
DIP Switch SW13
USB-to-UART Bridge
Figure 1-1: KC705 Board Block Diagram
shows the KC705 board. Each numbered feature that is referenced in
Figure 1-2
The image in
www.xilinx.com
Figure 1-1. The KC705 board schematics are
10/100/1000 Ethernet
Interface
JTAG Interface
mini-B USB Connector
is for reference only and might not reflect the current revision of the
Feature Descriptions
128 MB Linear BPI
Flash memory
128 Mb Quad-SPI
Flash Memory
8-lane PCI Express
Edge Connector
LCD Display
(2 line x 16 characters)
SFP+ Single Cage
UG810_c1_01_011812
Figure 1-2
9