Fpga Configuration - Xilinx ML623 User Manual

Chapter 1: ML623 Board Features and Operation
Technology Module is installed, place jumpers on JP1 and/or JP2 across pins 2–3 (OFF
position).
Note:
external supply to its corresponding supply jack.
The Texas Instruments and Intersil modules do not have voltage regulation jumpers and
must be removed from the board before providing external power to the GTX transceiver
rails.
Caution!
remove any jumper across J1 before powering the board with the Intersil module installed. Failure to
do so may damage the FPGA.

FPGA Configuration

[Figure
The FPGA is configured in JTAG mode only using one of the following options:
•
•
•
•
Detailed information on the System ACE controller is available in
DS080, System ACE CompactFlash Solution.
The FPGA is configured through one of the aforementioned cables by connecting the cable
to the download cable connector, J1.
The FPGA is configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card (see
Note:
cable is used, causing no disruption in the JTAG chain.
The JTAG chain of the board is illustrated in
isolation jumpers described in
on header J162 automatically bypasses the FMC modules and the GTX transceiver power
supply module in the chain.
14
The power regulation jumper must be placed in the OFF position before connecting an
The Intersil module features an MGTAVCC voltage adjust header, J1. Make sure to
1-2, callout 2]
Platform Cable USB
Parallel Cable IV
Parallel Cable III
System ACE controller
The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
www.xilinx.com
Configuration Address DIP Switches, page
Figure 1-5 (the four System ACE interface
JTAG Isolation Jumpers are not shown). Shorting pins 1 – 2
16).
ML623 Board User Guide
UG724 (v1.1) September 15, 2010