Watchdog Timer Module Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Introduction

Introduction

The watchdog timer is used to regain control when a system has failed due to a software error or due to

the failure of an external device to respond in the expected way. The M3 Subsystem has two watchdog

timer modules; one module is clocked by the system clock (Watchdog Timer 0) and the other is clocked

by the OSCCLK (Watchdog Timer 1). The two modules are identical except that WDT1 is in a different

clock domain, and therefore requires synchronizers. As a result, WDT1 has a bit defined in the watchdog

timer control (WDTCTL) register to indicate when a write to a WDT1 register is complete. Software can

use this bit to ensure that the previous access has completed before starting the next access.

The watchdog timer modules include the following features:

32-bit down counter with a programmable load register

Separate watchdog clock with an enable

Programmable interrupt generation logic with interrupt masking

Lock register protection from runaway software

Reset generation logic with an enable/disable

User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug

The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to

generate a reset signal on its second time-out. Once the watchdog timer has been configured, the lock

3.1.1 Block Diagram

The watchdog timer module block diagram is shown in

System Clock/

M3 Watchdog Timers

Figure 3-1. Watchdog Timer Module Block Diagram

Control /Clock/

Identification Registers

WDTPeriphID0

WDTPeriphID4

WDTPeriphID1

WDTPeriphID5

WDTPeriphID2

WDTPeriphID6

WDTPeriphID3

WDTPeriphID7

SPRUHE8E – October 2012 – Revised November 2019

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