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4 Functional Block Diagram
Figure 4-1
shows the MSPM0G350x functional block diagram.
CPU SUB SYSTEM
TRNG
IOMUX
SWCLK,
DEBUG
SWDIO
RTC_OUT
TX, RX,
UART0
CTS, RTS
TX, RX,
UART1
CTS, RTS
UART2
SDA, SCL
TIMG0
2-CH
2-CH
TIMG8
QEI/HALL
LEGEND
PD1, CPU ACCESS ONLY
PD1, CPU/DMA ACCESS
PD1/PD0, CPU/DMA ACCESS
PD0, CPU/DMA ACCESS
Copyright © 2023 Texas Instruments Incorporated
tIOBUSt
Arm
Cortex-M0+
f
= 80 MHz
max
NVIC
MPU
SWD + MTB
IOPORT
CPU-ONLY PD1 PERIPHERAL BUS (MCLK)
WWDT0
WWDT1
FLASHCTL
RTC
EVENT
PMCU (SYSCTL)
CKM
I2C0
SYSPLL
I2C1
LFOSC
SYSOSC
LFXT
HFXT
LFXIN, LFXOUT
HFXIN, HFXOUT
ROSC
CLK_OUT, FCC_IN
Figure 4-1. MSPM0G350x Functional Block Diagram
Product Folder Links:
MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
PAx, PBx
ULPCLK
GPIO
CAN-FD
FLASH
Up to 128KB
SRAM
Up to 32KB
DMA
7-ch
MATHACL
TIMG12
CRC
TEMP SENSOR
AES
12b ADC0
12b ADC1
PMU
GPAMP
LDO
BOR
12b DAC0
POR
COMP0
VBOOST
COMP1
COMP2
Each COMPx includes an 8b
reference DAC; COMP0 and
VDD, VSS
COMP1 reference DACs connect
VCORE, NRST
to OPA0 and OPA1, respectively
SLASF88 – OCTOBER 2023
TX, RX
TX, RX,
UART3
CTS, RTS
SPI0
POCI, PICO,
SPI1
SCK, CSx
4-CH
TIMA0
FAULT
2-CH
TIMA1
FAULT
TIMG6
2-CH
TIMG7
2-CH
2-CH
32-bit
A0_x
A1_x
ULPCLK
VREF+,
VREF
VREF-
OPA0
IN+, IN-,
OPA1
OUT
IN+, IN-,
OUT
DAC_OUT
IN+, IN-,
OUT
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