Sign In
Upload
Manuals
Brands
Texas Instruments Manuals
Microcontrollers
TMS320F28004x
Texas Instruments TMS320F28004x Manuals
Manuals and User Guides for Texas Instruments TMS320F28004x. We have
1
Texas Instruments TMS320F28004x manual available for free PDF download: Technical Reference Manual
Texas Instruments TMS320F28004x Technical Reference Manual (2254 pages)
Piccolo Microcontrollers
Brand:
Texas Instruments
| Category:
Microcontrollers
| Size: 11.66 MB
Table of Contents
Tms320F28004X Piccolo Microcontrollers Technical Reference Manual
2
Table of Contents
2
20
24
28
Preface
68
1 C28X Processor
69
Overview
70
Viterbi, Complex Math and CRC Unit (VCU)
71
System Control
73
Introduction
74
Power Management
74
Device Identification and Configuration Registers
75
Resets
75
Power-On Reset (POR)
76
Peripheral Interrupts
77
Interrupt Entry Sequence
78
Configuring and Using Interrupts
79
PIE Channel Mapping
81
Vector Tables
82
PIE Interrupt Vectors
83
Exceptions and Non-Maskable Interrupts
89
Illegal Instruction Trap (ITRAP)
90
Clocking
91
Using GPIO18 When INTOSC2 Is the SYSCLK Source
92
Single-Ended 3.3V External Clock
93
Derived Clocks
94
Xclkout
95
Clock Source and PLL Setup
97
Missing Clock Detection
99
32-Bit CPU Timers
101
Watchdog Timer
102
Minimum Window Check
103
Watchdog Operation in Low Power Modes
104
2.10 Low Power Modes
105
Halt
106
2.11 Memory Controller Module
108
Local Shared RAM
109
Arbitration Scheme on Global Shared Memories
110
Error Handling in Different Scenarios
113
Mapping of ECC Bits in Read Data from Ecc/Parity Address Map
114
2.12 Flash and OTP Memory
115
Default Flash Configuration
116
Flash and OTP and Wakeup Power-Down Modes
117
Flash and OTP Performance
118
Flash Prefetch Mode
119
Erase/Program Flash
121
Error Correction Code (ECC) Protection
122
Reserved Locations Within Flash and OTP
125
Dual Code Security Module (DCSM)
126
Security Levels
127
Storage of Zone-Select Bits in OTP
131
Location of Zone-Select Block Based on Link-Pointer for Bank0
132
Location of Zone-Select Block Based on Link-Pointer for Bank1
133
CSM Impact on Other On-Chip Resources
135
Incorporating Code Security in User Applications
137
CSM Password Match Flow (PMF)
138
ECSL Password Match Flow (PMF)
140
Registers
142
ACCESS_PROTECTION_REGS Registers
143
NMAVFLG Register
144
NMAVSET Register
145
NMAVCLR Register
146
NMAVINTEN Register
147
NMCPURDAVADDR Register
148
NMCPUWRAVADDR Register
149
NMCPUFAVADDR Register
150
NMDMAWRAVADDR Register
151
NMCLA1RDAVADDR Register
152
NMCLA1WRAVADDR Register
153
NMCLA1FAVADDR Register
154
MAVFLG Register
155
MAVSET Register
156
MAVCLR Register
157
MAVINTEN Register
158
MCPUFAVADDR Register
159
MCPUWRAVADDR Register
160
MDMAWRAVADDR Register
161
CLK_CFG_REGS Registers
162
CLKCFGLOCK1 Register
163
CLKSRCCTL1 Register
165
CLKSRCCTL2 Register
167
CLKSRCCTL3 Register
168
SYSPLLCTL1 Register
169
SYSPLLMULT Register
170
SYSPLLSTS Register
171
SYSCLKDIVSEL Register
172
XCLKOUTDIVSEL Register
173
LOSPCP Register
174
MCDCR Register
175
X1CNT Register
176
XTALCR Register
177
CPU_SYS_REGS Registers
178
CPUSYSLOCK1 Register
179
PIEVERRADDR Register
182
PCLKCR0 Register
183
PCLKCR2 Register
184
PCLKCR3 Register
186
PCLKCR4 Register
187
PCLKCR6 Register
188
PCLKCR7 Register
189
PCLKCR8 Register
190
PCLKCR9 Register
191
PCLKCR10 Register
192
PCLKCR13 Register
193
PCLKCR14 Register
194
PCLKCR15 Register
195
PCLKCR16 Register
196
PCLKCR17 Register
197
PCLKCR18 Register
198
PCLKCR19 Register
199
PCLKCR20 Register
200
PCLKCR21 Register
201
LPMCR Register
202
GPIOLPMSEL0 Register
203
GPIOLPMSEL1 Register
205
TMR2CLKCTL Register
207
RESCCLR Register
208
RESC Register
209
CPUTIMER_REGS Registers
211
TIM Register
212
PRD Register
213
TCR Register
214
TPR Register
216
TPRH Register
217
DCC_REGS Registers
218
DCCGCTRL Register
219
DCCREV Register
220
DCCCNTSEED0 Register
221
DCCVALIDSEED0 Register
222
DCCCNTSEED1 Register
223
DCCSTATUS Register
224
DCCCNT0 Register
225
DCCVALID0 Register
226
DCCCNT1 Register
227
DCCCLKSRC1 Register
228
DCCCLKSRC0 Register
229
Dcsm_Bank0_Z1_Regs Registers
230
B0_Z1_Linkpointer
231
Z1_Otpseclock
232
Z1_Bootdef_High
233
B0_Z1_Linkpointererr
234
Z1_Bootpin_Config
235
Z1_Gpreg2
236
Z1_Bootdef_Low
237
Z1_Csmkey0
238
Z1_Csmkey1
239
Z1_Csmkey2
240
Z1_Csmkey3
241
Z1_Cr
242
B0_Z1_Grabsectr
243
Z1_GRABRAMR Register
246
B0_Z1_EXEONLYSECTR Register
248
Z1_Exeonlyramr
251
Link Pointer Error for Flash Bank0/Dcsm_Bank0_Z2_Regs Registers
253
DCSM_BANK0_Z2_REGS Registers
253
Link Pointer Error for Flash BANK0
253
B0_Z2_LINKPOINTER Register
254
Z2_Otpseclock
255
B0_Z2_LINKPOINTERERR Register
256
Z2_Csmkey0
257
Z2_Csmkey1
258
Z2_Csmkey2
259
Z2_Csmkey3
260
Z2_Cr
261
B0_Z2_Grabsectr
262
Z2_GRABRAMR Register
265
B0_Z2_Exeonlysectr
267
Zone 2 Flash BANK0 Execute_Only Sector
267
Z2_EXEONLYRAMR Register
270
Zone 2 RAM Execute_Only Block Register
270
DCSM_BANK1_Z1_REGS Registers
272
B1_Z1_LINKPOINTER Register
273
B1_Z1_LINKPOINTERERR Register
274
B1_Z1_GRABSECTR Register
275
B1_Z1_EXEONLYSECTR Register
278
DCSM_BANK1_Z2_REGS Registers
281
B1_Z2_LINKPOINTER Register
282
B1_Z2_LINKPOINTERERR Register
283
B1_Z2_GRABSECTR Register
284
B1_Z2_EXEONLYSECTR Register
287
DCSM_COMMON_REGS Registers
290
FLSEM Register
291
B0_SECTSTAT Register
292
RAMSTAT Register
295
B1_SECTSTAT Register
297
SECERRSTAT Register
300
SECERRCLR Register
301
SECERRFRC Register
302
DCSM_COMMON2_REGS Registers
303
DEV_CFG_REGS Registers
304
PARTIDL Register
305
PARTIDH Register
306
REVID Register
307
FUSEERR Register
308
SOFTPRES0 Register
309
SOFTPRES2 Register
310
SOFTPRES3 Register
311
SOFTPRES4 Register
312
SOFTPRES6 Register
313
SOFTPRES7 Register
314
SOFTPRES8 Register
315
SOFTPRES9 Register
316
SOFTPRES10 Register
317
SOFTPRES13 Register
318
SOFTPRES14 Register
319
SOFTPRES15 Register
320
SOFTPRES16 Register
321
SOFTPRES17 Register
322
SOFTPRES18 Register
323
SOFTPRES19 Register
324
SOFTPRES20 Register
325
SOFTPRES21 Register
326
TAP_STATUS Register
327
DMA_CLA_SRC_SEL_REGS Registers
328
CLA1TASKSRCSELLOCK Register
329
DMACHSRCSELLOCK Register
330
CLA1TASKSRCSEL1 Register
331
CLA1TASKSRCSEL2 Register
332
DMACHSRCSEL1 Register
333
DMACHSRCSEL2 Register
334
FLASH_CTRL_REGS Registers
335
FRDCNTL Register
336
FBAC Register
337
FBFALLBACK Register
338
FBPRDY Register
339
FPAC1 Register
340
FPAC2 Register
341
FMSTAT Register
342
FRD_INTF_CTRL Register
344
FLASH_ECC_REGS Registers
345
ECC_ENABLE Register
346
SINGLE_ERR_ADDR_LOW Register
347
SINGLE_ERR_ADDR_HIGH Register
348
UNC_ERR_ADDR_LOW Register
349
UNC_ERR_ADDR_HIGH Register
350
ERR_STATUS Register
351
ERR_POS Register
353
ERR_STATUS_CLR Register
354
ERR_CNT Register
355
ERR_THRESHOLD Register
356
ERR_INTFLG Register
357
ERR_INTCLR Register
358
FDATAH_TEST Register
359
FDATAL_TEST Register
360
FADDR_TEST Register
361
FECC_TEST Register
362
FECC_CTRL Register
363
FOUTH_TEST Register
364
FOUTL_TEST Register
365
FECC_STATUS Register
366
MEM_CFG_REGS Registers
367
Dxlock Register
369
Dxcommit Register
370
Dxaccprot0 Register
371
Dxtest Register
372
Dxinit Register
373
Dxinitdone Register
374
Lsxlock Register
375
Lsxcommit Register
377
Lsxmsel Register
379
Lsxclapgm Register
381
Lsxaccprot0 Register
382
Lsxaccprot1 Register
384
Lsxtest Register
386
Lsxinit Register
388
Lsxinitdone Register
389
Gsxlock Register
390
Gsxcommit Register
391
Gsxaccprot0 Register
393
Gsxaccprot1 Register
395
Gsxaccprot2 Register
396
Gsxaccprot3 Register
397
Gsxtest Register
398
Gsxinit Register
400
Gsxinitdone Register
401
Msgxlock Register
402
Msgxcommit Register
403
Msgxtest Register
404
Msgxinit Register
405
Msgxinitdone Register
406
MEMORY_ERROR_REGS Registers
407
UCERRFLG Register
408
UCERRSET Register
409
UCERRCLR Register
410
UCCPUREADDR Register
411
UCDMAREADDR Register
412
UCCLA1READDR Register
413
CERRFLG Register
414
CERRSET Register
415
CERRCLR Register
416
CCPUREADDR Register
417
CERRCNT Register
418
CERRTHRES Register
419
CEINTFLG Register
420
CEINTCLR Register
421
CEINTSET Register
422
CEINTEN Register
423
NMI_INTRUPT_REGS Registers
424
NMICFG Register
425
NMIFLG Register
426
NMIFLGCLR Register
428
NMIFLGFRC Register
429
NMIWDCNT Register
430
NMIWDPRD Register
431
NMISHDFLG Register
432
Periph_Ac_Regs Registers
433
PERIPH_AC_REGS Access Type Codes
434
Adca_Ac
435
Adcb_Ac
436
Adcc_Ac
437
Cmpss1_Ac
438
Cmpss2_Ac
439
Cmpss3_Ac
440
Cmpss4_Ac
441
Cmpss5_Ac
442
Cmpss6_Ac
443
Cmpss7_Ac
444
Daca_Ac
445
Dacb_Ac
446
Pga1_Ac
447
Pga2_Ac
448
Pga3_Ac
449
Pga4_Ac
450
Pga5_Ac
451
Pga6_Ac
452
Pga7_Ac
453
Epwm1_Ac
454
Epwm2_Ac
455
Epwm3_Ac
456
Epwm4_Ac
457
Epwm5_Ac
458
Epwm6_Ac
459
Epwm7_Ac
460
Epwm8_Ac
461
Eqep1_Ac
462
Eqep2_Ac
463
Ecap1_Ac
464
Ecap2_Ac
465
Ecap3_Ac
466
Ecap4_Ac
467
Ecap5_Ac
468
Ecap6_Ac
469
Ecap7_Ac
470
Sdfm1_Ac
471
Clb1_Ac
472
Clb2_Ac
473
Clb3_Ac
474
Clb4_Ac
475
Cla1Promcrc_Ac
476
Spia_Ac
477
Spib_Ac
478
Pmbus_A_Ac
479
Lin_A_Ac
480
Dcana_Ac
481
Dcanb_Ac
482
Fsiatx_Ac
483
Fsiarx_Ac
484
HRPWM_A_AC Register
485
PERIPH_AC_LOCK Register
486
PIE_CTRL_REGS Registers
487
PIECTRL Register
488
PIEACK Register
489
PIEIER1 Register
490
PIEIFR1 Register
491
PIEIER2 Register
492
PIEIFR2 Register
493
PIEIER3 Register
494
PIEIFR3 Register
495
PIEIER4 Register
496
PIEIFR4 Register
497
PIEIER5 Register
498
PIEIFR5 Register
499
PIEIER6 Register
500
PIEIFR6 Register
501
PIEIER7 Register
502
PIEIFR7 Register
503
PIEIER8 Register
504
PIEIFR8 Register
505
PIEIER9 Register
506
PIEIFR9 Register
507
PIEIER10 Register
508
PIEIFR10 Register
509
PIEIER11 Register
510
PIEIFR11 Register
511
PIEIER12 Register
512
PIEIFR12 Register
513
ROM_PREFETCH_REGS Registers
514
ROMPREFETCH Register
515
ROM_WAIT_STATE_REGS Registers
516
ROMWAITSTATE Register
517
WD_REGS Registers
518
SCSR Register
519
WDCNTR Register
520
WDKEY Register
521
WDCR Register
522
WDWCR Register
524
XINT_REGS Registers
525
XINT1CR Register
526
XINT2CR Register
527
XINT3CR Register
528
XINT4CR Register
529
XINT5CR Register
530
XINT1CTR Register
531
XINT2CTR Register
532
XINT3CTR Register
533
3 ROM Code and Peripheral Booting
534
Introduction
535
Configuring Alternate Boot Mode Pins
536
Configuring Alternate Boot Mode Options
537
Boot Mode Example Use Cases
538
One Boot Pin Boot Table Result
539
Device Boot Flow Diagrams
540
Emulation Boot Flow Diagram
541
Standalone Boot Flow Diagram
542
Device Reset and Exception Handling
543
Boot ROM Description
544
Wait Points
545
ROM Tables
546
Boot Modes
547
Overview of SCI Bootloader Operation
548
Overview of SCI Boot Function
549
SPI Loader
549
SPI 8-Bit Data Stream
550
Data Transfer from EEPROM Flow
551
Overview of I2C Boot Function
552
Random Read
553
Sequential Read
554
Parallel GPIO Bootloader Handshake Protocol
555
Parallel GPIO Mode - Host Transfer Flow
556
Bit Parallel Getword Function
557
Overview of CAN-A Bootloader Operation
558
Boot Data Stream Structure
559
LSB/MSB Loading Sequence in 8-Bit Data Stream
560
GPIO Assignments
561
DCSM Usage
562
Clock Initialization
563
ROM Version
564
Application Notes for Using the Bootloaders
565
4 Control Law Accelerator (CLA)
567
Control Law Accelerator (CLA) Overview
568
CLA Block Diagram
569
CLA Interface
570
CLA Memory Bus
571
CLA Tasks and Interrupt Vectors
572
CLA Software Interrupt to CPU
575
CLA Configuration and Debug
577
Debugging CLA Code
579
CLA Illegal Opcode Behavior
580
Resetting the CLA
581
Pipeline
582
Write Followed by Read - Read Occurs First
583
ADC to CLA Early Interrupt Response
585
Parallel Instructions
586
Instruction Set
587
INSTRUCTION Dest, Source1, Source2 Short Description
588
Addressing Modes and Encoding
589
Shift Field Encoding
590
591
Instructions
591
MADDF32 Mrd, Mre, Mrf||Mmov32 Mem32, Mra 32-Bit Floating-Point Addition with Parallel Move
599
MADDF32 Mrd, Mre, Mrf ||MMOV32 Mra, Mem32 32-Bit Floating-Point Addition with Parallel Move
600
MAND32 Mra, Mrb, Mrc Bitwise and
602
MASR32 Mra, #SHIFT - Arithmetic Shift Right
603
MBCNDD 16Bitdest {, CNDF} - Branch Conditional Delayed
604
Pipeline Activity for MBCNDD, Branch Not Taken
606
MCCNDD 16Bitdest {, CNDF} - Call Conditional Delayed
609
Pipeline Activity for MCCNDD, Call Not Taken
612
MCLRC BGINTM - Clear Background Task Interrupt Mask
613
MCMPF32 Mra, Mrb - 32-Bit Floating-Point Compare for Equal, Less than or Greater than
615
MCMPF32 Mra, #16Fhi - 32-Bit Floating-Point Compare for Equal, Less than or Greater than
616
MDEBUGSTOP - Debug Stop Task
618
MDEBUGSTOP1 - Software Breakpoint
619
MEALLOW - Enable CLA Write Access to EALLOW Protected Registers
620
MEDIS - Disable CLA Write Access to EALLOW Protected Registers
621
MEINVF32 Mra, Mrb - 32-Bit Floating-Point Reciprocal Approximation
622
MEISQRTF32 Mra, Mrb - 32-Bit Floating-Point Square-Root Reciprocal Approximation
623
MF32TOI16 Mra, Mrb - Convert 32-Bit Floating-Point Value to 16-Bit Integer
624
MF32TOI16R Mra, Mrb - Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round
625
MF32TOUI16 Mra, Mrb - Convert 32-Bit Floating-Point Value to 16-Bit Unsigned Integer
627
MF32TOUI16R Mra, Mrb Convert 32-Bit Floating-Point Value to 16-Bit Unsigned Integer and Round
628
MF32TOUI32 Mra, Mrb - Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer
629
MFRACF32 Mra, Mrb - Fractional Portion of a 32-Bit Floating-Point Value
630
MI16TOF32 Mra, Mrb - Convert 16-Bit Integer to 32-Bit Floating-Point Value
631
Pipeline Activity for MMOV16 Marx, Mra , #16I
646
Pipeline Activity for MMOV16 MAR0/MAR1, Mem16
649
MMOV32 Mra, Mem32 {, CNDF} - Conditional 32-Bit Move
656
MMOV32 Mra, Mrb {, CNDF} - Conditional 32-Bit Move
658
MMOV32 MSTF, Mem32 - Move 32-Bit Value from Memory to the MSTF Register
660
MMOVD32 Mra, Mem32 - Move 32-Bit Value from Memory with Data Copy
661
MMOVF32 Mra, #32F - Load the 32-Bits of a 32-Bit Floating-Point Register
662
MMOVI16 Marx, #16I - Load the Auxiliary Register with the 16-Bit Immediate Value
663
Pipeline Activity for MMOVI16 MAR0/MAR1, #16I
663
MMOVI32 Mra, #32Fhex - Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate
664
MMOVIZ Mra, #16Fhi - Load the Upper 16-Bits of a 32-Bit Floating-Point Register
665
MMOVZ16 Mra, Mem16 - Load Mrx with 16-Bit Value
666
MMOVXI Mra, #16Flohex - Move Immediate to the Low 16-Bits of a Floating-Point Register
667
MMPYF32 Mra, Mrb, Mrc 32-Bit Floating-Point Multiply
668
MMPYF32 Mra, #16Fhi, Mrb 32-Bit Floating-Point Multiply
669
MMPYF32 Mra, Mrb, #16Fhi - 32-Bit Floating-Point Multiply
671
MMPYF32 Mrd, Mre, Mrf ||MMOV32 Mra, Mem32 - 32-Bit Floating-Point Multiply with Parallel Move
675
MMPYF32 Mrd, Mre, Mrf ||MMOV32 Mem32, Mra - 32-Bit Floating-Point Multiply with Parallel Move
677
MNEGF32 Mra, Mrb{, CNDF} Conditional Negation
679
MNOP - no Operation
681
MOR32 Mra, Mrb, Mrc - Bitwise or
682
MRCNDD {CNDF} - Return Conditional Delayed
683
Pipeline Activity for MRCNDD, Return Not Taken
685
MSETC BGINTM - Set Background Task Interrupt Mask
687
MSETFLG FLAG, VALUE - Set or Clear Selected Floating-Point Status Flags
688
MSTOP Stop Task
689
Pipeline Activity for MSTOP
690
MSUB32 Mra, Mrb, Mrc - 32-Bit Integer Subtraction
691
MSUBF32 Mra, Mrb, Mrc 32-Bit Floating-Point Subtraction
692
MSUBF32 Mra, #16Fhi, Mrb 32-Bit Floating-Point Subtraction
693
MTESTTF CNDF Test MSTF Register Flag Condition
698
Registers
705
CLA_ONLY_REGS Registers
706
MVECTBGRNDACTIVE Register
707
MPSACTL Register
708
MPSA1 Register
709
MPSA2 Register
710
SOFTINTEN Register
711
SOFTINTFRC Register
712
CLA_REGS Registers
713
MVECT1 Register
715
MVECT2 Register
716
MVECT3 Register
717
MVECT4 Register
718
MVECT5 Register
719
MVECT6 Register
720
MVECT7 Register
721
MVECT8 Register
722
MCTL Register
723
MVECTBGRNDACTIVE Register
724
SOFTINTEN Register
725
MSTSBGRND Register
726
MCTLBGRND Register
727
MVECTBGRND Register
728
MIFR Register
729
MIOVF Register
733
MIFRC Register
736
MICLR Register
738
MICLROVF Register
740
MIER Register
742
MIRUN Register
745
MPC Register
747
MAR0 Register
748
MAR1 Register
749
MSTF Register
750
MR0 Register
753
MR1 Register
754
MR2 Register
755
MR3 Register
756
MPSACTL Register
757
MPSA1 Register
758
MPSA2 Register
759
CLA_SOFTINT_REGS Registers
760
SOFTINTEN Register
761
SOFTINTFRC Register
762
CLA_PROM_CRC32_REGS Registers
763
CRC32_CONTROLREG Register
764
CRC32_STARTADDRESS Register
765
CRC32_SEED Register
766
CRC32_STATUSREG Register
767
CRC32_CRCRESULT Register
768
CRC32_GOLDENCRC Register
769
CRC32_INTEN Register
770
CRC32_FLG Register
771
CRC32_CLR Register
772
CRC32_FRC Register
773
5 CLA Program ROM (CLAPROMCRC)
774
Halt
776
6 General-Purpose Input/Output (GPIO)
777
GPIO Overview
778
Configuration Overview
779
Digital General-Purpose I/O Control
780
Synchronization to SYSCLK Only
781
Case 1: Three-Sample Sampling Window Width
782
Input Qualifier Clock Cycles
783
GPIO and Peripheral Muxing
784
Registers
786
GPIO_CTRL_REGS Registers
787
GPIO_CTRL_REGS Access Type Codes
788
GPACTRL Register
789
GPAQSEL1 Register
790
GPAQSEL2 Register
791
GPAMUX1 Register
792
GPAMUX2 Register
793
GPADIR Register
794
GPAPUD Register
796
GPAINV Register
798
GPAODR Register
800
GPAAMSEL Register
802
GPAGMUX1 Register
804
GPAGMUX2 Register
805
GPACSEL1 Register
806
GPACSEL2 Register
807
GPACSEL3 Register
808
GPACSEL4 Register
809
GPALOCK Register
810
GPACR Register
812
GPBCTRL Register
814
GPBQSEL1 Register
815
GPBQSEL2 Register
816
GPBMUX1 Register
817
GPBMUX2 Register
818
GPBDIR Register
819
GPBPUD Register
821
GPBINV Register
823
GPBODR Register
825
GPBGMUX1 Register
827
GPBGMUX2 Register
828
GPBCSEL1 Register
829
GPBCSEL2 Register
830
GPBCSEL3 Register
831
GPBCSEL4 Register
832
GPBLOCK Register
833
GPBCR Register
835
GPHCTRL Register
837
GPHQSEL1 Register
838
GPHQSEL2 Register
839
GPHINV Register
840
GPHAMSEL Register
842
GPHLOCK Register
844
GPHCR Register
846
GPIO_DATA_REGS Registers
848
GPADAT Register
849
GPASET Register
851
GPACLEAR Register
853
GPATOGGLE Register
855
GPBDAT Register
857
GPBSET Register
859
GPBCLEAR Register
861
GPBTOGGLE Register
863
GPHDAT Register
865
7 Crossbar (X-BAR)
867
GPIO Input X-BAR
868
Epwm and GPIO Output X-BAR
869
Epwm Architecture - Single Output
870
Epwm X-BAR Mux Configuration Table
871
GPIO Output X-BAR
872
X-BAR Flags
873
Epwm and Output X-Bars Sources
874
X-BAR Registers
875
INPUT_XBAR_REGS Registers
876
INPUT1SELECT Register
877
INPUT2SELECT Register
878
INPUT3SELECT Register
879
INPUT4SELECT Register
880
INPUT5SELECT Register
881
INPUT6SELECT Register
882
INPUT7SELECT Register
883
INPUT8SELECT Register
884
INPUT9SELECT Register
885
INPUT10SELECT Register
886
INPUT11SELECT Register
887
INPUT12SELECT Register
888
INPUT13SELECT Register
889
INPUT14SELECT Register
890
INPUT15SELECT Register
891
INPUT16SELECT Register
892
INPUTSELECTLOCK Register
893
XBAR_REGS Registers
895
XBARFLG1 Register
896
XBARFLG2 Register
901
XBARFLG3 Register
906
XBARFLG4 Register
910
XBARCLR1 Register
911
XBARCLR2 Register
914
XBARCLR3 Register
917
XBARCLR4 Register
919
EPWM_XBAR_REGS Registers
920
TRIP4MUX0TO15CFG Register
921
TRIP4MUX16TO31CFG Register
924
TRIP5MUX0TO15CFG Register
927
TRIP5MUX16TO31CFG Register
930
TRIP7MUX0TO15CFG Register
933
TRIP7MUX16TO31CFG Register
936
TRIP8MUX0TO15CFG Register
939
TRIP8MUX16TO31CFG Register
942
TRIP9MUX0TO15CFG Register
945
TRIP9MUX16TO31CFG Register
948
TRIP10MUX0TO15CFG Register
951
TRIP10MUX16TO31CFG Register
954
TRIP11MUX0TO15CFG Register
957
TRIP11MUX16TO31CFG Register
960
TRIP12MUX0TO15CFG Register
963
TRIP12MUX16TO31CFG Register
966
TRIP4MUXENABLE Register
969
TRIP5MUXENABLE Register
973
TRIP7MUXENABLE Register
977
TRIP8MUXENABLE Register
981
TRIP9MUXENABLE Register
985
TRIP10MUXENABLE Register
989
TRIP11MUXENABLE Register
993
TRIP12MUXENABLE Register
997
TRIPOUTINV Register
1001
TRIPLOCK Register
1003
OUTPUT_XBAR_REGS Registers
1004
OUTPUT1MUX0TO15CFG Register
1006
OUTPUT1MUX16TO31CFG Register
1009
OUTPUT2MUX0TO15CFG Register
1012
OUTPUT2MUX16TO31CFG Register
1015
OUTPUT3MUX0TO15CFG Register
1018
OUTPUT3MUX16TO31CFG Register
1021
OUTPUT4MUX0TO15CFG Register
1024
OUTPUT4MUX16TO31CFG Register
1027
OUTPUT5MUX0TO15CFG Register
1030
OUTPUT5MUX16TO31CFG Register
1033
OUTPUT6MUX0TO15CFG Register
1036
OUTPUT6MUX16TO31CFG Register
1039
OUTPUT7MUX0TO15CFG Register
1042
OUTPUT7MUX16TO31CFG Register
1045
OUTPUT8MUX0TO15CFG Register
1048
OUTPUT8MUX16TO31CFG Register
1051
OUTPUT1MUXENABLE Register
1054
OUTPUT2MUXENABLE Register
1058
OUTPUT3MUXENABLE Register
1062
OUTPUT4MUXENABLE Register
1066
OUTPUT5MUXENABLE Register
1070
OUTPUT6MUXENABLE Register
1074
OUTPUT7MUXENABLE Register
1078
OUTPUT8MUXENABLE Register
1082
OUTPUTLATCH Register
1086
OUTPUTLATCHCLR Register
1088
OUTPUTLATCHFRC Register
1090
OUTPUTLATCHENABLE Register
1092
OUTPUTINV Register
1094
OUTPUTLOCK Register
1096
8 Direct Memory Access (DMA)
1097
Introduction
1098
Architecture
1099
DMA Trigger Architecture
1100
Peripheral Interrupt Trigger Input Diagram
1101
Peripheral Interrupt Trigger Source Options
1102
DMA Bus
1103
CPU and CLA Arbitration
1104
Channel Priority
1105
Channel 1 High Priority Mode
1106
DMA State Diagram
1110
Overrun Detection Feature
1111
Registers
1112
DMA_REGS Registers
1113
DMACTRL Register
1114
DEBUGCTRL Register
1115
PRIORITYCTRL1 Register
1116
PRIORITYSTAT Register
1117
DMA_CH_REGS Registers
1118
MODE Register
1119
CONTROL Register
1121
BURST_SIZE Register
1123
BURST_COUNT Register
1124
SRC_BURST_STEP Register
1125
DST_BURST_STEP Register
1126
TRANSFER_SIZE Register
1127
TRANSFER_COUNT Register
1128
SRC_TRANSFER_STEP Register
1129
DST_TRANSFER_STEP Register
1130
SRC_WRAP_SIZE Register
1131
SRC_WRAP_COUNT Register
1132
SRC_WRAP_STEP Register
1133
DST_WRAP_SIZE Register
1134
DST_WRAP_COUNT Register
1135
DST_WRAP_STEP Register
1136
SRC_BEG_ADDR_SHADOW Register
1137
SRC_ADDR_SHADOW Register
1138
SRC_BEG_ADDR_ACTIVE Register
1139
SRC_ADDR_ACTIVE Register
1140
DST_BEG_ADDR_SHADOW Register
1141
DST_ADDR_SHADOW Register
1142
DST_BEG_ADDR_ACTIVE Register
1143
DST_ADDR_ACTIVE Register
1144
Analog Subsystem
1145
Analog Subsystem
1146
Analog Subsystem Block Diagram (100-Pin PZ LQFP)
1147
Analog Subsystem Block Diagram (64-Pin PM LQFP)
1148
Analog Subsystem Block Diagram (56-Pin RSH VQFN)
1149
Analog Group Connections
1150
Analog Pins and Internal Connections
1151
Analog Signal Descriptions
1153
Registers
1154
ASYS_REGS Registers
1155
ANAREFPP Register
1156
TSNSCTL Register
1157
ANAREFCTL Register
1158
DCDCCTL Register
1160
DCDCSTS Register
1161
CMPHPMXSEL Register
1162
CMPLPMXSEL Register
1164
CMPHNMXSEL Register
1166
CMPLNMXSEL Register
1167
LOCK Register
1168
Analog-To-Digital Converter (ADC)
1169
10 Analog-To-Digital Converter (ADC)
1170
ADC Block Diagram
1171
ADC Configurability
1172
SOC Principle of Operation
1173
SOC Block Diagram
1174
Input Model
1175
SOC Configuration Examples
1176
Example Requirements for Multiple Signal Sampling
1177
ADC Conversion Priority
1178
Round Robin Priority Example
1179
High Priority Example
1180
Burst Mode
1181
Burst Priority Example
1182
EOC and Interrupt Operation
1183
Post-Processing Blocks
1184
ADC PPB Interrupt Event
1186
Power-Up Sequence
1187
ADC Timings
1188
Additional Information
1189
Example 1: Basic Synchronous Operation
1190
Example 2: Synchronous Operation with Multiple Trigger Sources
1191
Example 3A: Synchronous Operation with Uneven SOC Numbers
1192
Choosing an Acquisition Window Duration
1193
Designing an External Reference Circuit
1194
Registers
1195
ADC_REGS Registers
1196
ADC_REGS Access Type Codes
1197
ADCCTL1 Register
1198
ADCCTL2 Register
1199
ADCBURSTCTL Register
1200
ADCINTFLG Register
1202
ADCINTFLGCLR Register
1204
ADCINTOVF Register
1206
ADCINTOVFCLR Register
1207
ADCINTSEL1N2 Register
1208
ADCINTSEL3N4 Register
1210
ADCSOCPRICTL Register
1212
ADCINTSOCSEL1 Register
1215
ADCINTSOCSEL2 Register
1217
ADCSOCFLG1 Register
1219
ADCSOCFRC1 Register
1223
ADCSOCOVF1 Register
1228
ADCSOCOVFCLR1 Register
1231
ADCSOC0CTL Register
1234
ADCSOC1CTL Register
1237
ADCSOC2CTL Register
1240
ADCSOC3CTL Register
1243
ADCSOC4CTL Register
1246
ADCSOC5CTL Register
1249
ADCSOC6CTL Register
1252
ADCSOC7CTL Register
1255
ADCSOC8CTL Register
1258
ADCSOC9CTL Register
1261
ADCSOC10CTL Register
1264
ADCSOC11CTL Register
1267
ADCSOC12CTL Register
1270
ADCSOC13CTL Register
1273
ADCSOC14CTL Register
1276
ADCSOC15CTL Register
1279
ADCEVTSTAT Register
1282
ADCEVTCLR Register
1283
ADCEVTSEL Register
1284
ADCEVTINTSEL Register
1286
ADCCOUNTER Register
1288
ADCREV Register
1289
ADCOFFTRIM Register
1290
ADCPPB1CONFIG Register
1291
ADCPPB1STAMP Register
1293
ADCPPB1OFFCAL Register
1294
ADCPPB1OFFREF Register
1295
ADCPPB1TRIPHI Register
1296
ADCPPB1TRIPLO Register
1297
ADCPPB2CONFIG Register
1298
ADCPPB2STAMP Register
1300
ADCPPB2OFFCAL Register
1301
ADCPPB2OFFREF Register
1302
ADCPPB2TRIPHI Register
1303
ADCPPB2TRIPLO Register
1304
ADCPPB3CONFIG Register
1305
ADCPPB3STAMP Register
1307
ADCPPB3OFFCAL Register
1308
ADCPPB3OFFREF Register
1309
ADCPPB3TRIPHI Register
1310
ADCPPB3TRIPLO Register
1311
ADCPPB4CONFIG Register
1312
ADCPPB4STAMP Register
1314
ADCPPB4OFFCAL Register
1315
ADCPPB4OFFREF Register
1316
ADCPPB4TRIPHI Register
1317
ADCPPB4TRIPLO Register
1318
ADCINTCYCLE Register
1319
ADC_RESULT_REGS Registers
1321
ADCRESULT0 Register
1322
ADCRESULT1 Register
1323
ADCRESULT2 Register
1324
ADCRESULT3 Register
1325
ADCRESULT4 Register
1326
ADCRESULT5 Register
1327
ADCRESULT6 Register
1328
ADCRESULT7 Register
1329
ADCRESULT8 Register
1330
ADCRESULT9 Register
1331
ADCRESULT10 Register
1332
ADCRESULT11 Register
1333
ADCRESULT12 Register
1334
ADCRESULT13 Register
1335
ADCRESULT14 Register
1336
ADCRESULT15 Register
1337
ADCPPB1RESULT Register
1338
ADCPPB2RESULT Register
1339
ADCPPB3RESULT Register
1340
ADCPPB4RESULT Register
1341
11 Programmable Gain Amplifier (PGA)
1342
Programmable Gain Amplifier (PGA) Overview
1343
Linear Output Range
1344
Error Calibration
1345
Ground Routing
1346
Lock Register
1347
Examples
1348
Cmpss
1349
Alternate Functions
1350
Registers
1351
PGA_REGS Registers
1352
PGACTL Register
1353
PGALOCK Register
1354
PGAGAIN3TRIM Register
1355
PGAGAIN6TRIM Register
1356
PGAGAIN12TRIM Register
1357
PGAGAIN24TRIM Register
1358
PGATYPE Register
1359
12 Buffered Digital-To-Analog Converter (DAC)
1360
Buffered Digital-To-Analog Converter (DAC) Overview
1361
Initialization Sequence
1362
DAC_REGS Registers
1363
DACREV Register
1364
DACCTL Register
1365
DACVALA Register
1366
DACVALS Register
1367
DACOUTEN Register
1368
DACLOCK Register
1369
DACTRIM Register
1370
Comparator Subsystem (CMPSS)
1371
CMPSS Overview
1372
Comparator
1373
Reference DAC Block Diagram
1374
Ramp Generator
1375
Ramp Generator Behavior at Corner Cases
1376
Digital Filter
1377
Using the CMPSS
1378
Registers
1379
CMPSS_REGS Registers
1380
COMPCTL Register
1381
COMPHYSCTL Register
1383
COMPSTS Register
1384
COMPSTSCLR Register
1385
COMPDACCTL Register
1386
DACHVALS Register
1388
DACHVALA Register
1389
RAMPMAXREFA Register
1390
RAMPMAXREFS Register
1391
RAMPDECVALA Register
1392
RAMPDECVALS Register
1393
RAMPSTS Register
1394
DACLVALS Register
1395
DACLVALA Register
1396
RAMPDLYA Register
1397
RAMPDLYS Register
1398
CTRIPLFILCTL Register
1399
CTRIPLFILCLKCTL Register
1400
CTRIPHFILCTL Register
1401
CTRIPHFILCLKCTL Register
1402
COMPLOCK Register
1403
Sigma Delta Filter Module (SDFM)
1404
SDFM Module Overview
1405
SDFM Features
1407
Block Diagram
1408
Sigma Delta Filter Module (SDFM) Block Diagram
1409
Block Diagram of One Filter Module
1411
Configuring Device Pins
1413
Primary (Data) Filter Unit
1414
Frequency Response of Various Primary (Data) Filters
1415
Bit or 16-Bit Data Filter Output Representation
1416
SDSYNC Event
1417
SDSYNC Event
1418
Secondary (Comparator) Filter Unit
1419
Data Rate and Latency of the Sinc Filter
1420
Interrupt Unit
1421
Drintx (Data-Ready Interrupt) Output Selection
1422
SDFM Interrupt Unit
1423
Registers
1424
SDFM_REGS Registers
1425
SDFM_REGS Access Type Codes
1426
SDIFLG Register
1427
SDIFLGCLR Register
1429
SDCTL Register
1431
SDMFILEN Register
1432
SDSTATUS Register
1433
SDCTLPARM1 Register
1434
SDDFPARM1 Register
1435
SDDPARM1 Register
1436
SDCMPH1 Register
1437
SDCMPL1 Register
1438
SDCPARM1 Register
1439
SDDATA1 Register
1440
SDDATFIFO1 Register
1441
SDCDATA1 Register
1442
SDCMPHZ1 Register
1443
SDFIFOCTL1 Register
1444
SDSYNC1 Register
1445
SDCTLPARM2 Register
1446
SDDFPARM2 Register
1447
SDDPARM2 Register
1448
SDCMPH2 Register
1449
SDCMPL2 Register
1450
SDCPARM2 Register
1451
SDDATA2 Register
1452
SDDATFIFO2 Register
1453
SDCDATA2 Register
1454
SDCMPHZ2 Register
1455
SDFIFOCTL2 Register
1456
SDSYNC2 Register
1457
SDCTLPARM3 Register
1458
SDDFPARM3 Register
1459
SDDPARM3 Register
1460
SDCMPH3 Register
1461
SDCMPL3 Register
1462
SDCPARM3 Register
1463
SDDATA3 Register
1464
SDDATFIFO3 Register
1465
SDCDATA3 Register
1466
SDCMPHZ3 Register
1467
SDFIFOCTL3 Register
1468
SDSYNC3 Register
1469
SDCTLPARM4 Register
1470
SDDFPARM4 Register
1471
SDDPARM4 Register
1472
SDCMPH4 Register
1473
SDCMPL4 Register
1474
SDCPARM4 Register
1475
SDDATA4 Register
1476
SDDATFIFO4 Register
1477
SDCDATA4 Register
1478
SDCMPHZ4 Register
1479
SDFIFOCTL4 Register
1480
SDSYNC4 Register
1481
15 Enhanced Pulse Width Modulator (Epwm)
1482
Introduction
1483
Submodule Overview
1484
Multiple Epwm Modules
1485
Submodules and Signal Connections for an Epwm Module
1486
Epwm Submodules and Critical Internal Signal Interconnects
1488
Configuring Device Pins
1489
Time-Base (TB) Submodule
1491
Time-Base Submodule Signals and Registers
1492
Time-Base Frequency and Period
1494
Time-Base Counter Synchronization Scheme
1496
Time-Base Up-Count Mode Waveforms
1498
Time-Base Down-Count Mode Waveforms
1499
Global Reload: Signals and Registers
1501
Counter-Compare (CC) Submodule
1502
Detailed View of the Counter-Compare Submodule
1503
Counter-Compare Event Waveforms in Up-Count Mode
1506
Counter-Compare Events in Down-Count Mode
1507
Action-Qualifier (AQ) Submodule
1508
Action-Qualifier Submodule
1509
Action-Qualifier Submodule Inputs and Outputs
1510
Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
1511
Action-Qualifier Event Priority for Up-Down-Count Mode
1512
Behavior if CMPA/CMPB Is Greater than the Period
1513
Aqctlr[Shdwaqamode]
1514
Up-Down-Count Mode Symmetrical Waveform
1516
Up-Down-Count, PWM Waveform Generation Utilizing T1 and T2 Events
1522
Dead-Band Generator (DB) Submodule
1523
Configuration Options for the Dead-Band Submodule
1525
Additional Dead-Band Operating Modes
1526
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
1527
Dead-Band Delay Values in Μs as a Function of DBFED and DBRED
1528
PWM Chopper (PC) Submodule
1529
PWM Chopper Submodule Operational Details
1530
Possible Pulse Width Values for EPWMCLK = 80 Mhz
1531
Trip-Zone (TZ) Submodule
1533
Possible Actions on a Trip Event
1535
Trip-Zone Submodule Mode Control Logic
1537
Event-Trigger (ET) Submodule
1538
Event-Trigger Submodule
1539
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
1540
Event-Trigger Interrupt Generator
1542
Event-Trigger SOCA Pulse Generator
1543
Digital Compare (DC) Submodule
1544
GPIO MUX-To-Trip Input Connectivity
1545
DCAEVT1 Event Triggering
1548
DCBEVT1 Event Triggering
1549
Event Filtering
1550
Epwm X-Bar
1551
Epwm X-Bar
1552
EPWM Architecture - Single Output
1553
Epwm X-BAR Mux Configuration Table
1554
Applications to Power Topologies
1555
Controlling Multiple Buck Converters with Independent Frequencies
1556
Controlling Multiple Buck Converters with same Frequencies
1558
Pwm1 )
1559
Pwm2 Pwm1
1559
Controlling Multiple Half H-Bridge (HHB) Converters
1560
Pwm1)
1561
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
1562
Practical Applications Using Phase Control between PWM Modules
1565
Controlling a 3-Phase Interleaved DC/DC Converter
1566
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
1569
Controlling a Peak Current Mode Controlled Buck Module
1570
Controlling H-Bridge LLC Resonant Converter
1571
Register Lock Protection
1572
Lock Bits and Corresponding Registers
1573
Registers
1574
EPWM_REGS Registers
1575
EPWM_REGS Access Type Codes
1576
TBCTL Register
1578
TBCTL2 Register
1580
TBCTR Register
1581
TBSTS Register
1582
CMPCTL Register
1583
CMPCTL2 Register
1585
DBCTL Register
1587
DBCTL2 Register
1590
AQCTL Register
1591
AQTSRCSEL Register
1593
PCCTL Register
1594
HRCNFG Register
1596
HRPWR Register
1598
HRMSTEP Register
1599
HRCNFG2 Register
1600
HRPCTL Register
1601
TRREM Register
1603
GLDCTL Register
1604
GLDCFG Register
1606
EPWMXLINK Register
1608
AQCTLA Register
1612
AQCTLA2 Register
1614
AQCTLB Register
1615
AQCTLB2 Register
1617
AQSFRC Register
1618
AQCSFRC Register
1619
DBREDHR Register
1620
DBRED Register
1621
DBFEDHR Register
1622
DBFED Register
1623
TBPHS Register
1624
TBPRDHR Register
1625
TBPRD Register
1626
CMPA Register
1627
CMPB Register
1628
CMPC Register
1629
CMPD Register
1630
GLDCTL2 Register
1631
TZSEL Register
1632
TZDCSEL Register
1634
TZCTL Register
1636
TZCTL2 Register
1638
TZCTLDCA Register
1640
TZCTLDCB Register
1642
TZEINT Register
1644
TZFLG Register
1645
TZCBCFLG Register
1647
TZOSTFLG Register
1648
TZCLR Register
1649
TZCBCCLR Register
1650
TZOSTCLR Register
1651
TZFRC Register
1652
ETSEL Register
1653
ETPS Register
1656
ETFLG Register
1659
ETCLR Register
1660
ETFRC Register
1661
ETINTPS Register
1662
ETSOCPS Register
1663
ETCNTINITCTL Register
1665
ETCNTINIT Register
1666
DCTRIPSEL Register
1667
DCACTL Register
1669
DCBCTL Register
1670
DCFCTL Register
1671
DCCAPCTL Register
1672
DCFOFFSET Register
1674
DCFOFFSETCNT Register
1675
DCFWINDOW Register
1676
DCFWINDOWCNT Register
1677
DCCAP Register
1678
DCAHTRIPSEL Register
1679
DCALTRIPSEL Register
1681
DCBHTRIPSEL Register
1683
DCBLTRIPSEL Register
1685
EPWMLOCK Register
1687
SYNC_SOC_REGS Registers
1688
SYNCSELECT Register
1689
ADCSOCOUTSELECT Register
1692
SYNCSOCLOCK Register
1694
16 High-Resolution Pulse Width Modulator (HRPWM)
1695
Introduction
1696
Resolution for PWM and HRPWM
1697
Operational Description of HRPWM
1698
HRPWM Extension Registers and Memory Configuration
1699
HRPWM System Interface
1700
Configuring the HRPWM
1701
Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay
1702
Required PWM Waveform for a Requested Duty = 40.5
1703
CMPA Vs Duty (Left), and [CMPA:CMPAHR] Vs Duty (Right)
1704
Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)
1706
Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles
1707
High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)
1708
Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)
1709
Deadband High Resolution Operation
1712
Scale Factor Optimizing Software (SFO)
1713
Simple Buck Controlled Converter Using a Single PWM
1714
Simple Reconstruction Filter for a PWM-Based DAC
1716
Appendix A: SFO Library Software - Sfo_Ti_Build_V7.Lib
1719
Software Usage
1720
17 Enhanced Capture (Ecap)
1722
Introduction
1723
Configuring Device Pins for the Ecap
1724
Capture and APWM Operating Mode
1725
Capture Mode Description
1726
Event Prescaler
1727
Edge Polarity Select and Qualifier
1728
Bit Counter and Phase Control
1729
CAP1-CAP4 Registers
1730
Interrupt Control
1731
Interrupts in Ecap Module
1733
DMA Interrupt
1734
Application of the ECAP Module
1735
Capture Sequence for Absolute Time-Stamp and Rising Edge Detect
1736
Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger
1738
Example 3 - Time Difference (Delta) Operation Rising Edge Trigger
1740
Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger
1742
Application of the APWM Mode
1744
Registers
1746
ECAP_REGS Registers
1747
TSCTR Register
1748
CTRPHS Register
1749
CAP1 Register
1750
CAP2 Register
1751
CAP3 Register
1752
CAP4 Register
1753
ECCTL0 Register
1754
ECCTL1 Register
1755
ECCTL2 Register
1757
ECEINT Register
1760
ECFLG Register
1761
ECCLR Register
1762
ECFRC Register
1763
18 High Resolution Capture (HRCAP)
1764
Introduction to the HRCAP Module
1765
HRCAP Clocking
1766
HRCAP Interrupts
1767
Driverlib Functions
1768
Registers
1769
HRCAP_REGS Registers
1770
HRCTL Register
1771
HRINTEN Register
1772
HRFLG Register
1773
HRCLR Register
1774
HRFRC Register
1775
HRCALPRD Register
1776
HRSYSCLKCTR Register
1777
HRSYSCLKCAP Register
1778
HRCLKCTR Register
1779
HRCLKCAP Register
1780
19 Enhanced QEP (Eqep)
1781
Introduction
1782
Index Pulse Example
1783
Configuring Device Pins
1784
Functional Description
1785
Eqep Memory Map
1786
Quadrature Decoder Unit (QDU)
1787
Quadrature Decoder State Machine
1788
Quadrature-Clock and Direction Decoding
1789
Eqep Input Polarity Selection
1790
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0Xf9F)
1791
Position Counter Latch
1792
Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)
1793
Position Counter Initialization
1794
Eqep Position-Compare Unit
1795
Eqep Edge Capture Unit
1796
Eqep Edge Capture Unit
1798
Eqep Edge Capture Unit - Timing Details
1799
Eqep Watchdog
1800
QMA Module
1801
QMA Mode-1
1802
QMA Mode-2
1803
Interrupt and Error Generation
1804
Registers
1805
EQEP_REGS Registers
1806
QPOSCNT Register
1807
QPOSINIT Register
1808
QPOSMAX Register
1809
QPOSCMP Register
1810
QPOSILAT Register
1811
QPOSSLAT Register
1812
QPOSLAT Register
1813
QUTMR Register
1814
QUPRD Register
1815
QWDTMR Register
1816
QWDPRD Register
1817
QDECCTL Register
1818
QEPCTL Register
1819
QCAPCTL Register
1822
QPOSCTL Register
1823
QEINT Register
1824
QFLG Register
1826
QCLR Register
1828
QFRC Register
1830
QEPSTS Register
1832
QCTMR Register
1833
QCPRD Register
1834
QCTMRLAT Register
1835
QCPRDLAT Register
1836
REV Register
1837
QEPSTROBESEL Register
1838
QMACTRL Register
1839
20 Serial Peripheral Interface (SPI)
1840
SPI Module Overview
1841
System-Level Integration
1842
Configuring Device Pins
1843
SPI Interrupt Flags and Enable Logic Generation
1844
DMA Support
1845
Master Mode
1846
Slave Mode
1847
Data Format
1848
Baud Rate Selection
1849
SPI Clocking Schemes
1850
SPI FIFO Description
1851
SPI DMA Transfers
1852
SPI High-Speed Mode
1853
SPI 3-Wire Master Mode
1854
Programming Procedure
1855
Configuring the SPI for High-Speed Mode
1856
SPI STEINV Bit in Digital Audio Transfers
1857
SPI Digital Audio Receiver Configuration Using Two Spis
1858
Registers
1859
SPI_REGS Registers
1860
SPICCR Register
1861
SPICTL Register
1863
SPISTS Register
1865
SPIBRR Register
1867
SPIRXEMU Register
1868
SPIRXBUF Register
1869
SPITXBUF Register
1870
SPIDAT Register
1871
SPIFFTX Register
1872
SPIFFRX Register
1874
SPIFFCT Register
1876
SPIPRI Register
1877
Serial Communications Interface (SCI)
1878
Enhanced SCI Module Overview
1879
Serial Communications Interface (SCI) Module Block Diagram
1880
Architecture
1881
SCI Programmable Data Format
1882
Recognizing the Address Byte
1883
Idle-Line Mode Steps
1884
Block Start Signal
1885
SCI Communication Format
1886
Receiver Signals in Communication Modes
1887
SCI Port Interrupts
1888
SCI Baud Rate Calculations
1889
SCI FIFO Interrupt Flags and Enable Logic
1890
SCI Auto-Baud
1891
Registers
1892
SCI_REGS Registers
1893
SCICCR Register
1894
SCICTL1 Register
1896
SCIHBAUD Register
1898
SCILBAUD Register
1899
SCICTL2 Register
1900
SCIRXST Register
1901
SCIRXEMU Register
1903
SCIRXBUF Register
1904
SCITXBUF Register
1905
SCIFFTX Register
1906
SCIFFRX Register
1908
SCIFFCT Register
1910
SCIPRI Register
1911
22 Inter-Integrated Circuit Module (I2C)
1912
Introduction to the I2C Module
1913
Functional Overview
1914
Clock Generation
1915
I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
1916
Configuring Device Pins
1917
I2C Module START and STOP Conditions
1918
Serial Data Formats
1919
I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR)
1920
NACK Bit Generation
1921
Clock Synchronization
1922
Digital Loopback Mode
1923
Interrupt Requests Generated by the I2C Module
1924
I2C FIFO Interrupts
1925
Resetting or Disabling the I2C Module
1926
Registers
1927
I2C_REGS Registers
1928
I2COAR Register
1929
I2CIER Register
1930
I2CSTR Register
1931
I2CCLKL Register
1935
I2CCLKH Register
1936
I2CCNT Register
1937
I2CDRR Register
1938
I2CSAR Register
1939
I2CDXR Register
1940
I2CMDR Register
1941
I2CISRC Register
1945
I2CEMDR Register
1946
I2CPSC Register
1947
I2CFFTX Register
1948
I2CFFRX Register
1949
23 Power Management Bus Module (Pmbus)
1950
Introduction
1951
Functional Description
1952
Message Handling
1953
Send Byte Message with and Without PEC
1954
Write Byte and Write Word Messages with and Without PEC
1955
Read Byte and Read Word Messages with and Without PEC
1956
Process Call Message with and Without PEC
1957
Block Read Message with and Without PEC
1958
Alert Response Message
1959
Extended Command Write Byte and Write Word Messages with and Without PEC
1960
Master Mode Operation
1961
Message Handling
1962
Write Byte and Write Word Messages with and Without PEC
1963
Read Byte and Read Word Messages with and Without PEC
1964
Block Write Message with and Without PEC
1965
Block Read Message with and Without PEC
1966
Alert Response Message
1967
Extended Command Read Message with and Without PEC
1968
Group Command Message with and Without PEC
1969
Registers
1970
PMBUS_REGS Registers
1971
PMBMC Register
1972
PMBTXBUF Register
1973
PMBRXBUF Register
1974
PMBACK Register
1975
PMBSTS Register
1976
PMBINTM Register
1978
PMBSC Register
1979
PMBHSA Register
1981
PMBCTRL Register
1982
PMBTIMCTL Register
1984
PMBTIMCLK Register
1985
PMBTIMSTSETUP Register
1986
PMBTIMBIDLE Register
1987
PMBTIMLOWTIMOUT Register
1988
PMBTIMHIGHTIMOUT Register
1989
24 Controller Area Network (CAN)
1990
Overview
1991
Block Diagram
1992
Configuring Device Pins
1993
Operating Modes
1994
CAN Message Transfer (Normal Operation)
1995
Test Modes
1996
CAN Core in Loopback Mode
1997
Multiple Clock Source
1998
Message Object Interrupts
1999
Parity Check Mechanism
2000
Configuration of Message Objects
2001
Configuration of a Single Receive Object for Remote Frames
2002
Message Handling
2003
Updating a Transmit Object
2004
Reception of Data Frames
2005
Requesting New Data for a Receive Object
2006
CAN Bit Timing
2007
Bit Time and Bit Rate
2008
The Propagation Time Segment
2009
Synchronization on Late and Early Edges
2011
Configuration of the CAN Bit Timing
2012
Structure of the CAN Core's CAN Protocol Controller
2013
Message Interface Register Sets
2015
Message Interface Register Sets 1 and 2
2016
IF3 Register Set
2017
Message RAM
2018
Addressing Message Objects in RAM
2020
Message RAM Representation in Debug Mode
2021
Registers
2022
CAN_REGS Registers
2023
CAN_REGS Access Type Codes
2024
CAN_CTL Register
2025
CAN_ES Register
2027
CAN_ERRC Register
2029
CAN_BTR Register
2030
CAN_INT Register
2031
CAN_TEST Register
2032
CAN_PERR Register
2033
CAN_RAM_INIT Register
2034
CAN_GLB_INT_EN Register
2035
CAN_GLB_INT_FLG Register
2036
CAN_GLB_INT_CLR Register
2037
CAN_ABOTR Register
2038
CAN_TXRQ_X Register
2039
CAN_TXRQ_21 Register
2040
CAN_NDAT_X Register
2041
CAN_NDAT_21 Register
2042
CAN_IPEN_X Register
2043
CAN_IPEN_21 Register
2044
CAN_MVAL_X Register
2045
CAN_MVAL_21 Register
2046
CAN_IP_MUX21 Register
2047
CAN_IF1CMD Register
2048
CAN_IF1MSK Register
2051
CAN_IF1ARB Register
2052
CAN_IF1MCTL Register
2053
CAN_IF1DATA Register
2055
CAN_IF1DATB Register
2056
CAN_IF2CMD Register
2057
CAN_IF2MSK Register
2060
CAN_IF2ARB Register
2061
CAN_IF2MCTL Register
2062
CAN_IF2DATA Register
2064
CAN_IF2DATB Register
2065
CAN_IF3OBS Register
2066
CAN_IF3MSK Register
2068
CAN_IF3ARB Register
2069
CAN_IF3MCTL Register
2070
CAN_IF3DATA Register
2072
CAN_IF3DATB Register
2073
CAN_IF3UPD Register
2074
25 Local Interconnect Network (LIN) Module
2075
Introduction and Features
2076
Block Diagram
2077
SCI Block Diagram
2078
LIN Communication Formats
2079
Message Frame
2080
Response Format of LIN Message Frame
2081
Synchronizer
2082
Header Generation
2083
Message Header in Terms of T
2084
Measurements for Synchronization
2086
Synchronization Validation Process and Baud Rate Adjustment
2087
Extended Frames Handling
2088
Timeout Control
2089
TXRX Error Detector (TED)
2090
TXRX Error Detector
2091
Classic Checksum Generation at Transmitting Node
2092
Message Filtering and Validation
2093
ID Reception, Filtering and Validation
2094
Receive Buffers
2095
Transmit Buffers
2096
LIN Interrupts
2097
Interrupt Generation for Given Flags
2098
Servicing Interrupts
2099
LIN Configurations
2101
Transmitting Data
2102
LIN Low-Power Mode
2103
Wakeup Signal Generation
2104
Registers
2105
LIN_REGS Registers
2106
SCIGCR0 Register
2107
SCIGCR1 Register
2108
SCIGCR2 Register
2113
SCISETINT Register
2115
SCICLEARINT Register
2120
SCISETINTLVL Register
2125
SCICLEARINTLVL Register
2129
SCIFLR Register
2133
SCIINTVECT0 Register
2142
SCIINTVECT1 Register
2143
SCIFORMAT Register
2144
BRSR Register
2145
SCIED Register
2146
SCIRD Register
2147
SCITD Register
2148
SCIPIO0 Register
2149
SCIPIO2 Register
2150
LINCOMP Register
2151
LINRD0 Register
2152
LINRD1 Register
2153
LINMASK Register
2154
LINID Register
2155
LINTD0 Register
2156
LINTD1 Register
2157
MBRSR Register
2158
IODFTCTRL Register
2159
LIN_GLB_INT_EN Register
2162
LIN_GLB_INT_FLG Register
2163
LIN_GLB_INT_CLR Register
2164
26 Fast Serial Interface (FSI)
2165
Introduction to the FSI Module
2166
FSI Transmitter (FSITX) CPU Interface
2167
Signal Description
2168
Interrupts
2169
CLA Task Triggering
2171
FSI Operation
2172
FSI Transmitter Block Diagram
2173
FSI Transmitter Core Block Diagram
2174
FSI Receiver Module
2178
FSI Receiver Block Diagram
2179
FSI Receiver Core Block Diagram
2180
Delay Line Control Circuit
2183
Frame Format
2185
Frame Types and Their 4-Bit Codes
2186
Ping Frame
2187
The Flush Sequence
2188
Internal Loopback
2189
ECC Module
2190
Point to Point Connection
2191
Register Protection
2192
Registers
2193
FSI_RX_REGS Registers
2194
RX_MASTER_CTRL Register
2196
RX_OPER_CTRL Register
2197
RX_FRAME_INFO Register
2198
RX_FRAME_TAG_UDATA Register
2199
RX_DMA_CTRL Register
2200
RX_EVT_STS Register
2201
RX_CRC_INFO Register
2204
RX_EVT_CLR Register
2205
RX_EVT_FRC Register
2207
RX_BUF_PTR_LOAD Register
2209
RX_BUF_PTR_STS Register
2210
RX_FRAME_WD_CTRL Register
2211
RX_FRAME_WD_REF Register
2212
RX_FRAME_WD_CNT Register
2213
RX_PING_WD_CTRL Register
2214
RX_PING_TAG Register
2215
RX_PING_WD_REF Register
2216
RX_PING_WD_CNT Register
2217
RX_INT1_CTRL Register
2218
RX_INT2_CTRL Register
2220
RX_LOCK_CTRL Register
2222
RX_ECC_DATA Register
2223
RX_ECC_VAL Register
2224
RX_ECC_SEC_DATA Register
2225
RX_ECC_LOG Register
2226
RX_DLYLINE_CTRL Register
2227
RX_VIS_1 Register
2228
RX_BUF_BASE Register
2229
FSI_TX_REGS Registers
2230
TX_MASTER_CTRL Register
2231
TX_CLK_CTRL Register
2232
TX_OPER_CTRL_LO Register
2233
TX_OPER_CTRL_HI Register
2234
TX_FRAME_CTRL Register
2235
TX_FRAME_TAG_UDATA Register
2236
TX_BUF_PTR_LOAD Register
2237
TX_BUF_PTR_STS Register
2238
TX_PING_CTRL Register
2239
TX_PING_TAG Register
2240
TX_PING_TO_REF Register
2241
TX_PING_TO_CNT Register
2242
TX_INT_CTRL Register
2243
TX_DMA_CTRL Register
2245
TX_LOCK_CTRL Register
2246
TX_EVT_STS Register
2247
TX_EVT_CLR Register
2248
TX_EVT_FRC Register
2249
TX_USER_CRC Register
2250
TX_ECC_DATA Register
2251
TX_ECC_VAL Register
2252
TX_BUF_BASE Register
2253
Advertisement
Advertisement
Related Products
Texas Instruments TMS320F28068
Texas Instruments TMS320F28069
Texas Instruments TMS320F28065
Texas Instruments TMS320F28064
Texas Instruments TMS320F28067
Texas Instruments TMS320F28063
Texas Instruments TMS320F28062
Texas Instruments TMS320F28066
Texas Instruments TMS320F2807 Series
Texas Instruments TMS320F280039C
Texas Instruments Categories
Motherboard
Control Unit
Microcontrollers
Computer Hardware
Calculator
More Texas Instruments Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL