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2.4
ADC Clock Source Options
The ADS126x requires a master clock to operate the delta-sigma modulator. The clock frequency, f
directly proportional to the modulator's sampling rate, f
rate follows the modulator sampling rate divided by the overall decimation ratio set by the digital filter. This
clock can be supplied by the ADS126x internal oscillator, by the X1 crystal oscillator on the ADS126xEVM,
or by an external clock source. The clock source is determined by switch S1 and jumper JP2.
shows the relevant clocking circuitry on the ADS126xEVM.
Figure 9. A) Schematic of ADS126xEVM Clocking Circuitry and B) Clocking Components on the
Use one of the following clocking options:
1. Onboard 7.3728 MHz Crystal Oscillator (Default Configuration)
The ADS126xEVM has an onboard crystal oscillator (component X1). The crystal oscillator clock is
detected by the ADS126x when switch S1 is in the 1-2 position (switched to the right, as shown in
Figure
9B).
2. ADS126x Internal 7.3728 MHz Oscillator
The ADS126x selects the internal oscillator when no external clock is detected. To use this mode,
ground the XTAL1/CLKIN input by switching S1 to the 2-3 position (switched to the left) and float the
XTAL2 input by shorting jumper JP2.
3. External Clock Source
If an alternate clock source or frequency is preferred, apply the external clock to the XTAL1/CLKIN
input, and float XTAL2. The ADS126xEVM provides for this external clock connection. Remove jumper
JP2 and apply the clock to the JP2 jumper posts. Configure switch S1 to the 2-3 position (switched to
the left). The external clock source must have a frequency between 1 MHz and 8 MHz, and have a
peak-to-peak amplitude equal to the DVDD supply voltage.
SBAU206 – April 2015
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A)
ADS126xEVM
Copyright © 2015, Texas Instruments Incorporated
(= f
/8). Consequently, the ADC output data
MOD
CLK
B)
ADS126xEVM Hardware
, is
CLK
Figure 9
11
ADS126xEVM-PDK
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