Digital Interface, J1; J1, Serial Interface Header - Texas Instruments ADS126 EVM-PDK Series User Manual

ADS126xEVM Hardware
2.5

Digital Interface, J1

The J1 header (top) and socket (bottom) provide access to the digital controls and serial data pins of the
ADS126x. These signals can be connected to a development platform for software development. All logic
levels are referenced to the digital supply voltage (the MMB0 provides a 3.3-V digital supply to the
ADS126xEVM through pin J5.9).
Function
Unused
SPI clock
Unused
Serial port active low chip
select (100-kΩ pull-up)
Unused
Serial port data input
Serial port data output and
data ready indicator (active
low)
Data ready indicator (active
low)
Unused
Unused
NOTE: Keep all connections to the ADS126xEVM as short as possible. If jumper wiring is used to
connect a software development board to the ADS126xEVM, keep a ground connection
(wire) between boards close to all of the digital signals (wires). A large loop area between
ground and digital signals creates inductive connections and poor signal integrity.
When probing SPI communications, check the signal integrity near the receiving end (that is,
probe DIN at the ADS126x input, not at the SPI controller output).
12
ADS126xEVM-PDK
Table 3 describes the J1 serial interface pins.
Table 3. J1, Serial Interface Header
Pin Number
Signal Name (J1)
1
SCLK 3
5
CS 7
9
DIN 11
DOUT/DRDY 13
DRDY 15
17
19
Copyright © 2015, Texas Instruments Incorporated
Signal Name
2
START
4 GND
6
RESET/PWDN
8
10 GND
12
14
16
SCL
18 GND
20 SDA
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Function
Start conversion control
(100-kΩ pull-up)
Ground
Reset (active low) or hold
low to power-down the
ADC (100-kΩ pull-up)
Unused
Ground
Unused
Unused
2
I C clock (for EEPROM)
Ground
2
I C data (for EEPROM)
SBAU206 – April 2015