Evm Clock Input Options - Texas Instruments ADS62P EVM Series User Manual

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EVM Option Evaluation Goal
Evaluate ADC
1 performance using a
sinusoid clock
Evaluate ADC
performance using a
2 crystal filtered LVCMOS
clock derived from
CDCE72010
Evaluate ADC
performance using a
3
differential LVCEPL
clock
2.2.4.1 Clock Option 1
The Clock Option 1 provides a clock to ADC directly from an external source. For the direct supply of the
clock to the ADC, a single-ended square or sinusoidal clock input must be applied to J19. The clock
frequency must be within the maximum frequency specified for the ADC. The clock input is converted to a
differential signal by a Mini-Circuits™ ADT4-1WT, which has an impedance ratio of 4, implying that
voltage applied on J19 is stepped up by a factor of 2. ADC performance in this case depends on the clock
source quality. This option is also the default configuration on the EVM, when it is shipped from the
factory. The test result using this option is shown in
2.2.4.2 Clock Option 2
Option 2 uses the onboard VCXO and CDCE72010 to provide a clock to the ADC. The CDCE72010 is
used in SPI mode which uses the internal EEPROM to configure the CDCE72010. The EEPROM is
programmed in the factory for a divide-by-4 configuration. The EEPROM configuration is shown in
Figure 4. The clock at J19 is the reference clock for CDCE72010. The VCXO frequency can be calculated
as Fvcxo = Fout x 4 (Fout is the frequency output U0 and U1). The reference clock for CDCE72010 is
calculated from Ref Clock = (Fvcxo x 125)/(48 x 128). This is the clock-to-M divider. When VCXO of
frequency 983.04 MHz is used, the calculation results in a reference clock of 20 MHz; the clock output on
Y0 pin of CDCE72010 is 245.76 MHz. This clock is filtered using the crystal filter with center frequency of
245.76 MHz. By default, the VCXO and the crystal filter are not populated on the EVM, so that the user
can populate the components depending on the end application and sampling rate. This configuration is
recommended for applications requiring an onboard clock generation scheme. The test result using this
option is shown in
SLAU237A – May 2008 – Revised April 2009
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Table 7. EVM Clock Input Options
Jumper Changes
Required
J18 → 2-3
SJP4 → 1-2
SJP7 → 1-2
SJP6 → 1-2
J14 → 1-2
J15 → No shunt
J18 → 1-2
SJP4 → 2-3
SJP7 → 3-4
SJP6 → 1-2
J14 → No Shunt
J15 → No Shunt
J18 → 1-2
SJP4 → 2-3
SJP7 → 5-6
SJP6 → 2-3
J14 → No Shunt
J15 → No Shunt
Figure 11.
Frequency Input CDC Configuration
on J19 Description
ADC's Sampling
Frequency
20M for VCXO at Divide VCXO frequency
983.04 MHz by 4, output on Y0
Divide VCXO frequency
20M for VCXO at by 4, differential
983.04 MHz LVPECL Clock output
on Y1P and Y1N
Figure 10.
Circuit Description
Comments
NA Default
Maximum
performance
Not
recommended for
most applications
ADS62PXXEVM 15