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Signal
I/O
Default
Name
Type
Mode
GPIO53
I/O
Native
2
GPIO54
I/O
Native
GPIO55
I/O
Native
GPIO56
I/O
Native
GPIO57
I/O
GPI
SML1CLK/
I/O
SML1CL
GPIO58
K
OC0#/
I/O
OC0#
2
GPIO59
®
®
Intel
Xeon
Processor E3-1125C with Intel
User Guide
50
Ball
Default
Power
Coun
Direction
Well
t
and Logic
State
1
O (High)
CORE
1
I
CORE
1
O (High)
CORE
1
I
SUS
1
I
SUS
1
I
SUS
1
I
SUS
®
Communications Chipset 8910 Development Kit
Crystal Forest—Technical Reference
Internal/
External
Resistor Pull-
Up/Down
Platform
General Purpose I/O Port 53. Not
Dependant. Weak
Multiplexed.
internal pull-up
External platform dependent.
DMI Coupling Strap.
0 AC Coupling (Pull-Down Required)
1 DC Coupling (Default)
General Purpose I/O Port 54. Not
Multiplexed
Weak internal
General Purpose I/O Port 55. Not
pull-up
Multiplexed.
Strap for BIOS Boot-Block Update
Scheme. This mode allows the PCH to
swap the Top-Block in the SPI (the boot
block) with another location.
GPIO55
0 Enable Top-Block Swap (Pull-down
required)
1 Disable Top-Block Swap (Default)
The internal pull-up is disabled after
PLTRST# deasserts. If the signal is
sampled low, this indicates that the
system is strapped to the "Top-Block
Swap" mode (the PCH inverts A16 for all
cycles targeting BIOS space).
The status of this strap is readable via
the Top Swap bit (Chipset Config
Registers:Offset 3414h:bit 0). Software
will not be able to clear the Top-Swap bit
until the system is rebooted without
GPIO55 being pulled down.
General Purpose I/O Port 56. Not
Multiplexed.
General Purpose I/O Port 57. Not
Multiplexed.
When SMBUS:
System Management Link 1 Clock.
External pull-up
SMBus link to external BMC.
required
External pull-up resistor to VCCSUS3P3 is
required.
Resistor value should be calculated based
on the bus load, refer to the Platform
Design Guide.
If SML1CLK interface is not used, the
signals can be used as GPIO Port 58.
Overcurrent Indicators. These signals set
corresponding bits in the USB controllers
to indicate that an overcurrent condition
has occurred.
OC[3:0]# may optionally be used as
GPIO Ports [42,41,40,59].
OC# pins are 3.3V and NOT 5 V tolerant.
OC# pins must be shared between ports
OC#[3:0] can only be used for EHCI
controller #1
Description
3
3
3
3
continued...
October 2012
Order No.: 328009-001US
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