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Signal
I/O
Default
Name
Type
Mode
SLOAD/
I/O
GPI
GPIO38
SDATAOU
I/O
GPI
T0/
GPIO39
OC1#/
I/O
OC1#
2
GPIO40
OC2#/
I/O
OC2#
2
GPIO41
OC3#/
I/O
OC3#
2
GPIO42
®
®
Intel
Xeon
Processor E3-1125C with Intel
User Guide
48
Ball
Default
Power
Coun
Direction
Well
t
and Logic
State
1
I
CORE
1
I
CORE
1
I
SUS
1
I
SUS
1
I
SUS
®
Communications Chipset 8910 Development Kit
Crystal Forest—Technical Reference
Internal/
External
Resistor Pull-
Up/Down
triggers memory controller of CPU to put
SDRAM into self-refresh mode. Activation
of ADR flushes contents of some write
data buffers to the DIMM before self
refresh entry.
SATA Serial GPIO Load. The controller
drives a '1' at the rising edge of SCLOCK
to indicate either the start or end of a bit
stream. A 4-bit vendor specific pattern
will be transmitted right after the signal
assertion.
If SLOAD interface is not used, this signal
can be used as a GPIO Port 38.
SATA Serial GPIO Data Out 0. Driven by
the controller to indicate the drive status
in the following sequence: drive 4,
5...4,5...
If SDATAOUT0 interface is not used, this
signal can be used as a GPIO Port 39.
Overcurrent Indicators. These signals set
corresponding bits in the USB controllers
to indicate that an overcurrent condition
has occurred.
OC[3:0]# may optionally be used as
GPIO Ports [42,41,40,59].
Note:
1. OC# pins are 3.3V and NOT 5V
tolerant
2. OC# pins must be shared between
ports
3. OC#[3:0] can only be used for EHCI
controller #1
Overcurrent Indicators. These signals set
corresponding bits in the USB controllers
to indicate that an overcurrent condition
has occurred.
OC[3:0]# may optionally be used as
GPIO Ports [42,41,40,59].
Note:
1. OC# pins are 3.3V and NOT 5V
tolerant
2. OC# pins must be shared between
ports
3. OC#[3:0] can only be used for EHCI
controller #1
Overcurrent Indicators. These signals set
corresponding bits in the USB controllers
to indicate that an overcurrent condition
has occurred.
OC[3:0]# may optionally be used as
GPIO Ports [42,41,40,59].
Note:
1. OC# pins are 3.3V and NOT 5V
tolerant
2. OC# pins must be shared between
ports
Description
continued...
October 2012
Order No.: 328009-001US
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