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Signal
I/O
Default
Name
Type
Mode
2
GPIO10
I/O
Native
MST_SMB
I/O
MST_SM
ALERT#/
BALERT
2
GPIO11
#
GPIO12
I/O
Native
4
GPIO13
I/O
GPI
GPIO14
I/O
Native
GPIO15
I/O
GPO
SATA4_GP
I/O
GPI
/GPIO16
GPIO17
I/O
GPI
GPIO18
I/O
Native
GPIO19
I/O
GPI
GPIO20
I/O
Native
GPIO21
I/O
GPI
SCLOCK/
I/O
GPI
GPIO22
LDRQ1#/
I/O
LDRQ1#
GPIO23
®
®
Intel
Xeon
Processor E3-1125C with Intel
User Guide
46
Ball
Default
Power
Coun
Direction
Well
t
and Logic
State
1
I
SUS
1
I
SUS
1
O (Low)
SUS
1
I
SUS
1
I
SUS
1
O (Low)
SUS
1
I
CORE
1
I
CORE
1
I
CORE
1
I
CORE
1
I
CORE
1
I
CORE
1
I
CORE
1
I
CORE
®
Communications Chipset 8910 Development Kit
Crystal Forest—Technical Reference
Internal/
External
Resistor Pull-
Up/Down
General Purpose I/O Port 9. Not
Multiplexed
External pull-up
SUS
required
SMBus Alert. This signal is used to wake
the system or generate SMI#. External
pull-up resistor to VCCSUS3P3 is
required.
Resistor value should be calculated based
on the bus load, see the Platform Design
Guide. This signal can also be configured
to GPIO Port 11.
General Purpose I/O Port 12. Not
Multiplexed.
Weak internal
General Purpose I/O Port 13. Not
pull-down
Multiplexed
General Purpose I/O Port 14. Not
Multiplexed
General Purpose I/O Port 15. Not
Multiplexed
Serial ATA 4 General Purpose. This is an
input pin which can be configured as an
interlock switch corresponding to SATA
Port 4. When used as an interlock switch
status indication, this signal should be
drive to '0' to indicate that the switch is
closed and to '1' to indicate that the
switch is open.
If interlock switches are not required, this
pin can be configured as GPIO port 16
Platform
General Purpose I/O Port 17. Not
Dependent
Multiplexed. This signal strapping sets
the DMI termination voltage.
General Purpose I/O Port 18. Not
Multiplexed
General Purpose I/O Port 19. Not
Multiplexed.
General Purpose I/O Port 20. Not
Multiplexed.
General Purpose I/O Port 21. Not
Multiplexed.
SGPIO Reference Clock. The SATA
controller uses rising edges of this clock
to transmit serial data, and the target
uses the falling edge of this clock to latch
data.
If SCLOCK interface is not used, this
signal can be used as a GPIO Port 22.
LPC Serial DMA/Master Request Input Bit
1. Used by LPC devices, such as Super I/
O chips, to request DMA or bus master
access. This signal is typically connected
Description
3
3
3
3
continued...
October 2012
Order No.: 328009-001US
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