Vih, Vil, Tperiod, % Duty Cycle; Tstable; Tx Characterization Dut Test Setup - Nvidia Jetson AGX Orin Series Compliance Manual

Vih, Vil, Tperiod, % Duty Cycle

Use the measurement functions for these parameters.

Take more than 1,000 measurements.

See specifications for Vih, Vil, Tperiod<10.203ns, Average Accuracy, and Duty Cycle.


Tstable

Use Min. Neg. Width and Pos. Width, set the mid ref level at -150 mV or +150 mV respectively
for the measurement. Alternatively, the trigger level can be set to -150 mV and +150 mV and
an infinite persistence measurement can be taken of the minimum for each. Take more than
1,000 measurements. See specification for Tstable.

Tx Characterization DUT Test Setup

For REFCLK, see notes regarding REFCLK characterization. In case Tx test is executed for a
PCÍe device (which means that Orin was taken off the PCB) and Orin is providing REFCLK to
the device, then use the breakout board to inject compliant REFCLK through appropriate
solder pads (Orin side) to the DUT.
For the Tx test setup, the following soldering pads of the removed device must be identified to
test DUT Tx lane-n (each Tx lane will be tested separately one by one for each single preset
starting with lane-0 with [lane-0 < lane-n < lane-m], where m for lane-m is 0 for x1, 3 for x4
and 7 for x8) and n in [0..m]. Also locate soldering pads for REFCLK+, nearest GND to
REFCLK+, REFCLK- and nearest GND to REFCLK-. Solder down breakout boards.
Tx Lane-n+, nearest GND to lane-n+
Tx Lane-n-, nearest GND to lane-n-
Rx Lane-n+, nearest GND to lane-n+
Rx Lane-n-, nearest GND to lane-n-
RefCLK+, nearest GND to RefCLK+
RefCLK-, nearest GND to RefCLK-
PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide
PCIe Compliance Testing Reference
Breakout board #1
Breakout board #2
Breakout board #3
DA-11040-001_v0.7 | 20