Cables; Probes; Mode Pulse Generation - Nvidia Jetson AGX Orin Series Compliance Manual

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Cables

It is important when probing to use the lowest loss cables possible. For PCIe data lanes (and
REFCLK differential measurement), high-quality SMA cables must be used along with short
SMA-SMB cables (when needed). This is to probe the differential data signal taping into a
breakout board soldered to the PCB exhibiting an SMA connector. Cables, connectors, and
termination such as SMA (male)-SMA (male) cable, SMA (female)-SMP cable, SMP-SMP, SMA
male connector to SMP female connector and so on. SMP 50 Ω termination resistors shall be
good for 25 GHz or greater.

Probes

Probes are used to connect the oscilloscope and BERT to the test fixture or probing points.
Special adapters (breakout boards) and solder tips for probes may be required depending on
selected setup. The following probes may be required:
2× high Impedance and high-bandwidth probes (single-ended) for REFCLK stand
measurements.
50 Ω differential probes for REFCLK differential measurement and PCIe Rx and Tx lane
characterization.

Mode Pulse Generation

For Tx measurement, a 100 MHz and 1 ms pulse must be injected into the corresponding Rx
lane-n of the Tx lane-n to be characterized. Each single mode pulse will switch the Tx lane into
the subsequent preset. The default Tx preset after power-up will be Gen1. For this purpose,
either a PCI-SIG CBB stand-alone, or a signal generator may be used. Here is a brief overview
as to how to use a CBB as mode pulse generator for this purpose:
Set clock source to internal; use internal oscillator to generate pulse. See the area circled
1.
in yellow in Figure 2.
Connect CBB J5/J85 to Rx lane-n P+ / P- of DUT
2.
Connect ATX power supply to connector
3.
Fix CBB in a stand or holder
4.
Use push button to issue pulse to step through presets. See the area circled in blue in
5.
Figure 2
PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide
PCIe Compliance Testing Reference
DA-11040-001_v0.7 | 13

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