Measuring Logic - Fluke PM6690 Service Manual

2
Figure 6-97
I C bus activity - reading the temperature.
2
n
The I C Bus in the '90'
The processor is the Master on the I
are:
•
The digital I/O IC U40 with address 20hex. It controls
the relays and filters in the input amplifiers.
•
The temperature measuring IC U39 with address
48hex.
•
The digital I/O IC U3 with address 21hex. It switches
the LCD display on after power-on initialization, it
scans the keyboard on the display circuit board.
The bus is connected to the prescaler connector J15 for future
use.
See Figure 6-97 and Figure 6-98.

Measuring Logic

The measurements are made in the FPGA. Only four
interpolators are external to the FPGA. They increase the ba-
sic measurement resolution from 10 ns (100 MHz measure-
ment clock) to less than 100 ps. Different combinations of
interpolators are used for different measurement functions;
two, three or four in conjunction. The input signals come from
the input amplifiers. A, B and SR are differential LVPECL in-
SDA
HIGH
TEMP
SDA
LOW
TEMP
SCL
2
C bus. Slaves on the bus
2
Figure 6-98
I C bus activity - depressing the EXIT key.
puts. C, the prescaler input, is a single-ended LVTTL input.
The measuring logic also provides three LEDs on the front
panel with control signals.
The interpolator transforms a pulse width between 20 and
33 ns to a voltage. This voltage is read by an ADC. The
interpolator is calibrated by reference pulses having a width
of 20 and 30 ns . The measurement pulse varies between 22
and 32 ns typically. The ADC has two reference voltages, the
lower limit and the upper limit. The interpolated voltage must
never fall outside these limits.
Select the default setting from the front panel. Apply a
10 MHz sinewave signal (stable low jitter signal) to input A.
The signal should be found at the pins of the FPGA. Check
that the measurement signal is present on pins 10 and 11 (dif-
ferential input) on the FPGA U11.The trigger indicator LED
A on the front panel should blink. The gate indicator on the
front panel should also blink and the display should show the
measurement result. In this setting the S/R flip-flop U12 is
used. Check that the measurement signal is present on pins 45
and 46 (differential input) on the FPGA U11.
Move the 10 MHz sinewave signal to input B. Change the
measurement function to Frequency B. Check that the mea-
surement signal is present on pins 20 and 21 (differential in-
put) on the FPGA U11. The trigger level LED B and the gate
indicator LED should blink and the display should show the
measurement result.
SCL
SDA
Troubleshooting 6-55