Prescalers; Microprocessor & Memories - Fluke PM6690 Service Manual

locked, and the VCO will go to one of the extremes. The typi-
cal range of the VCO is 95 to 105 MHz, thus giving an error of
typically 5 % in the measuring results.
Check the loop voltage (DC) at R272. It should be 1.6 - 2.2 V.
Check the 100 MHz signal at U48:4. It should be locked to the
incoming 10 MHz at U9:8. Check the lock condition with a
2-channel oscilloscope. Trigger on the 10 MHz channel. Then
the signal on the other channel shall be fixed, i.e. not moving
along the time axis. Check the PLL LOCK signal at U9:14
(lock is high).

Prescalers

The optional prescalers are not to be repaired. The faulty unit
should be sent to the factory, and an exchange unit will be
returned.
The best way to isolate the fault is to use another, functioning,
timer/counter with the same prescaler. Interchange the
prescalers and see if the problem follows the prescaler or the
timer/counter.
First measure with Channels A and B and check that the result
is OK. Select the function Frequency C. Connect a signal ac-
cording to Table 6-2 to Input C. Check the following pins on
the prescaler connector J15 on the main circuit board.
Pin 1 +5 V supply
Pin 5 +12 V supply
Pin 7 ON/OFF, ON is 0 V
Pin 11 test signal, should be 0 V
Pin 12 code 0, see Table 6-2
Pin 14 code 1, see Table 6-2
Pin 16 code 2, see Table 6-2
Pin 4 prescaler output signal, PECL levels (+4.1 V and
+3.4 V)
3 GHz
Frequency (GHz) 1
Level (dBm) 0
Division Factor 16
Code 0 0
Code 1 1
Code 2 0
Table 6-2
Prescaler characteristics.
Measure with oscilloscope and probe at pin 4. The output fre-
quency should be the input frequency divided by the factor in
the table. Check with a frequency counter.
Note: The 3 GHz option has a sensitivity trimmer. See page
7-14 for information on how to adjust it.
OPTION
8 GHz 14 GHz
1 5
0 0
256 128
0 1
0 0
1 1
Microprocessor & Memories
Startup Process
The processor in this instrument is a 32-bit ARM7TDMI. It is
housed in an IC (U13) together with peripheral units (SRAM,
2
timers, I C bus interface, SPI bus interface, LCD controller
etc). The complete IC is a Triscend design and of type A7S20.
A separate memory bus on the processor is connected to one
16-bit Flash PROM (U17) and two 16-bit SDRAMs (U16 and
U15). The two SDRAMs are connected to form a 32-bit wide
memory.
A Reset IC (U116) monitors +3.3 VD, +2.5 V and +1.8V. The
reset signal is active low and kept low for approximately 160
to 180 ms after the voltages are OK. Measure at X33. The
ramp-up time for +3.3 VD is approximately 2 ms, for 2.5 V
approximately 4 ms and for 1.8 V approximately 3 ms.
The rising edge of the reset signal marks the start of the boot
sequence. All I/Os on the processor are set high with a weak
(high-ohmic) pull-up. The fan will run at full speed (R492).
The memory controller in the processor is set up. The proces-
sor reads in the Flash PROM for the initialization data at cer-
tain addresses. Check CE0 at U13 pin 16. When the data is
found, the processor loads it inside the processor IC. The I/Os
will be set up. The fan will stop running because the pin is set
low. The 32 kHz oscillator will start running (check at R357)
and an internal PLL will generate 30 MHz internal and exter-
nal clock, check X29.
After the initialization the processor starts executing code
from address 0 in the Flash PROM. The program copies the
code from the Flash PROM to the SDRAM. When done it
starts executing from the SDRAM. Check SDCE0 at U13:26.
The Flash is not used for executing code after this, only occa-
sionally for storing data that should be non-volatile.
See Figure 6-21 to Figure 6-23 for a survey of a typical instru-
ment startup.
The LCD is switched on. The LCD controller in the processor
generates the control signals for the LCD. See Figure 6-24 to
Figure 6-29. Note the different timing for the signals. The I
bus is used for switching the LCD on. The ON signal can be
checked at R34 on the display board. It should be high. The
LCD voltages must also be switched on. It is done by a control
signal from the processor. Check the signal at R33 on the dis-
play board. It should be high. Negative pulses on this signal
are used for adjusting the contrast of the LCD, i.e. the LCD
voltages. The range is 14.9 V to 17.5 V measured at X1 on the
display board. Set the contrast so X1 is 16.2 V. Check the
LCD voltages at X2 (14.7 V), X3 (13.3 V), X4 (2.9 V) and X5
(1.5 V). See Figure 6-19.
The FPGA (U11) has to be programmed. The I
for controlling the loading of the FPGA, the pins PROGN
(U40:9) INITN (U40:7) and DONE (U40:8) are used. The
clock (U11:155) and data (U11:153) are controlled by the
2
C
2
C bus is used
Troubleshooting 6-15