Measuring Logic - Fluke PM6690 Service Manual

2
Figure 6-46
I C bus activity - reading the temperature.

Measuring Logic

The measurements are made in the FPGA. Only four
interpolators are external to the FPGA. They increase the ba-
sic measurement resolution from 10 ns (100 MHz measure-
ment clock) to less than 100 ps. Different combinations of
interpolators are used for different measurement functions;
two, three or four in conjunction. The input signals come from
the input amplifiers. A, B and SR are differential LVPECL in-
puts. C, the prescaler input, is a single-ended LVTTL input.
The measuring logic also provides three LEDs on the front
panel with control signals.
The interpolator transforms a pulse width between 20 and
33 ns to a voltage. This voltage is read by an ADC. The
interpolator is calibrated by reference pulses having a width of
20 and 30 ns . The measurement pulse varies between 22 and
32 ns typically. The ADC has two reference voltages, the
lower limit and the upper limit. The interpolated voltage must
never fall outside these limits.
Select the default setting from the front panel. Apply a
10 MHz sinewave signal (stable low jitter signal) to input A.
The signal should be found at the pins of the FPGA. Check
that the measurement signal is present on pins 17 and 18 (dif-
SDA
NORM.
TEMP
SDA
LOW
TEMP
SCL
Figure 6-47
ferential input) on the FPGA U11.The trigger indicator LED
A on the front panel should blink. The gate indicator on the
front panel should also blink and the display should show the
measurement result. In this setting the S/R flip-flop U12 is
used. Check that the measurement signal is present on pins 30
and 31 (differential input) on the FPGA U11.
Move the 10 MHz sinewave signal to input B. Change the
measurement function to Frequency B. Check that the mea-
surement signal is present on pins 20 and 21 (differential in-
put) on the FPGA U11. The trigger level LED B and the gate
indicator LED should blink and the display should show the
measurement result.
Move the 10 MHz sinewave signal back to input A. Change
the measurement function to Period Single A. Now the S/R
flip-flop should not be used, check the control signal at R623,
it should be -1.6 V (on is -1.0 V). Select statistics. The std de-
viation should be less than 100 ps.
Change the measurement function to Time Interval A - A. Se-
lect Statistics Mode. Check that the standard deviation is less
than 100 ps. Measure at pin 8 of the ADCs U23, U22, U21
and U20. Two types are current, ADC10461 and ADC1061.
See Figure 6-49 for a typical timing diagram with
ADC10461. Figure 6-50 shows an example with ADC1061.
Check the upper (TP3) and lower (TP4) voltage limits of the
ADCs. They should be approximately 3.5 - 3.6 V and 1.1 - 1.4
V. The important thing is that the lowest voltage pulse on any
2
I C bus activity - depressing the EXIT key.
Troubleshooting 6-27
SDA
SCL